Simulation Results

Simulation Results: i2c

12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.68 %

code
85.68 %

assert
97.46 %

func
79.90 %

block
95.95 %

line
95.29 %

branch
92.73 %

toggle
72.68 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	53.000s	1485.523us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	12.000s	4608.883us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	66.908us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	20.628us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.000s	662.647us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	30.843us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	39.472us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	20.628us	1	1	100.00
	i2c_csr_aliasing	2.000s	30.843us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	153.483us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	294.000s	11777.498us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	11.000s	3031.157us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	28.043us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3601.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1668.000s	2509.793us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	501.038us	1	1	100.00
	i2c_host_fifo_fmt_empty	13.000s	351.136us	1	1	100.00
	i2c_host_fifo_reset_rx	4.000s	212.896us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	312.000s	11407.688us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	10.000s	492.749us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	211.663us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.000s	965.544us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	39.000s	8498.552us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	558.732us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	19.000s	9325.283us	1	1	100.00
	i2c_target_intr_smoke	6.000s	5147.645us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	138.303us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	218.988us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	12.000s	18333.825us	1	1	100.00
	i2c_target_stress_rd	19.000s	9325.283us	1	1	100.00
	i2c_target_intr_stress_wr	8.000s	2929.919us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.000s	2200.044us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	12.000s	1928.674us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	457.867us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.000s	166.588us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	512.770us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	103.073us	1	1	100.00
host_mode_config_perf				1	2	50.00
	i2c_host_perf	11.000s	3031.157us	1	1	100.00
	i2c_host_perf_precise	3600.000s	0.000us	0	1	0.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	10.000s	492.749us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	7.000s	546.129us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	6.000s	606.359us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	1188.668us	1	1	100.00
	i2c_target_nack_txstretch	2.000s	397.968us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.000s	2016.127us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	5.000s	470.392us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	19.067us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	15.676us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	121.567us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	121.567us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	66.908us	1	1	100.00
	i2c_csr_rw	2.000s	20.628us	1	1	100.00
	i2c_csr_aliasing	2.000s	30.843us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	29.429us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	66.908us	1	1	100.00
	i2c_csr_rw	2.000s	20.628us	1	1	100.00
	i2c_csr_aliasing	2.000s	30.843us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	29.429us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	79.182us	1	1	100.00
	i2c_sec_cm	1.000s	112.159us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	79.182us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	16.000s	1111.481us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	73.265us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	18.000s	1592.910us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	63722273538159178347677986377721025991759577892208416168480763255712990468575	97	UVM_INFO @ 153483242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	41452390435824036586963823386417872131754294899603581891100204706710109551265	122	UVM_INFO @ 11777497860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	90765639748670748030138332736159112972475763746536092020070453748638006394860	122	UVM_INFO @ 1592910219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	i2c_host_fifo_watermark	5005420153303962756418000647420709110830547407401640444065672476884840119612	None
	i2c_host_perf_precise	76533395033381358592180109403550425195898054487307299753157357107360208809775	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	93639260411462197370870483903802555666954999799676979609891646903511751027794	93	UVM_INFO @ 965544256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	750896925717611848688906845011880209989437235794762500571081874105028283501	87	UVM_INFO @ 73265384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	60459196314668284350979403384384319231806902814367432672858294199790689573603	116	UVM_INFO @ 1111481097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	67541265580825182644448715937203691279258233451781707333153819696182772173725	94	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @17097