Simulation Results: lc_ctrl/volatile_unlock_disabled

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.57 %
  • code
  • 93.04 %
  • assert
  • 95.97 %
  • func
  • 88.71 %
  • block
  • 96.61 %
  • line
  • 97.32 %
  • branch
  • 91.38 %
  • toggle
  • 88.23 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 38.800us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 21.960us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 98.536us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 54.577us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 52.711us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 20.326us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 98.536us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 52.711us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 88.416us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 997.813us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 12.778us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 46.799us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 815.346us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 664.951us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 815.346us 1 1 100.00
lc_ctrl_prog_failure 2.000s 46.799us 1 1 100.00
lc_ctrl_errors 6.000s 664.951us 1 1 100.00
lc_ctrl_security_escalation 4.000s 304.405us 1 1 100.00
lc_ctrl_jtag_state_failure 18.000s 2878.480us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 212.261us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 9437.941us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.000s 422.795us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 853.036us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 212.261us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 9437.941us 1 1 100.00
lc_ctrl_jtag_access 3.000s 1098.458us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.000s 4412.098us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 68.326us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 64.859us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.000s 1894.303us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 478.973us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 72.524us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 1302.576us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 70.841us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 832.001us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 35.378us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 31.000s 5066.977us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 50.875us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 44.198us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 44.198us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 21.960us 1 1 100.00
lc_ctrl_csr_rw 1.000s 98.536us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 52.711us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 177.427us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 21.960us 1 1 100.00
lc_ctrl_csr_rw 1.000s 98.536us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 52.711us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 177.427us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 219.197us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 50.169us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 50.169us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 997.813us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 815.346us 1 1 100.00
lc_ctrl_sec_cm 3.000s 219.197us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 815.346us 1 1 100.00
lc_ctrl_sec_cm 3.000s 219.197us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 815.346us 1 1 100.00
lc_ctrl_sec_cm 3.000s 219.197us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 815.346us 1 1 100.00
lc_ctrl_sec_cm 3.000s 219.197us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 815.346us 1 1 100.00
lc_ctrl_sec_cm 3.000s 219.197us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 815.346us 1 1 100.00
lc_ctrl_sec_cm 3.000s 219.197us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 815.346us 1 1 100.00
lc_ctrl_sec_cm 3.000s 219.197us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 815.346us 1 1 100.00
lc_ctrl_sec_cm 3.000s 219.197us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 304.405us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 88.416us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 853.036us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 498.546us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 498.546us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 371.075us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1705.082us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1705.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 30.000s 27878.264us 1 1 100.00