Simulation Results: lc_ctrl/volatile_unlock_enabled

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.97 %
  • code
  • 93.69 %
  • assert
  • 96.40 %
  • func
  • 85.81 %
  • block
  • 97.07 %
  • line
  • 97.63 %
  • branch
  • 92.56 %
  • toggle
  • 86.96 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.000s 196.105us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 82.371us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 123.791us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 146.977us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.578us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 213.642us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 123.791us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 350.171us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 718.849us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 12.483us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 69.239us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 1564.722us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 944.738us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 1564.722us 1 1 100.00
lc_ctrl_prog_failure 2.000s 69.239us 1 1 100.00
lc_ctrl_errors 5.000s 944.738us 1 1 100.00
lc_ctrl_security_escalation 5.000s 410.281us 1 1 100.00
lc_ctrl_jtag_state_failure 24.000s 12413.928us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 904.674us 1 1 100.00
lc_ctrl_jtag_errors 9.000s 11007.722us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 303.670us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 3911.808us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 904.674us 1 1 100.00
lc_ctrl_jtag_errors 9.000s 11007.722us 1 1 100.00
lc_ctrl_jtag_access 5.000s 2376.267us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 3974.500us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 674.911us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 166.207us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.000s 756.706us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.000s 1170.939us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 30.493us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 1115.025us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 554.711us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 672.430us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 42.761us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 6.000s 4304.872us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 18.045us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 72.660us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 72.660us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 82.371us 1 1 100.00
lc_ctrl_csr_rw 1.000s 123.791us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.578us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 83.679us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 82.371us 1 1 100.00
lc_ctrl_csr_rw 1.000s 123.791us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 17.578us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 83.679us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 228.671us 1 1 100.00
lc_ctrl_tl_intg_err 1.000s 248.856us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.000s 248.856us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 718.849us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1564.722us 1 1 100.00
lc_ctrl_sec_cm 3.000s 228.671us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1564.722us 1 1 100.00
lc_ctrl_sec_cm 3.000s 228.671us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1564.722us 1 1 100.00
lc_ctrl_sec_cm 3.000s 228.671us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1564.722us 1 1 100.00
lc_ctrl_sec_cm 3.000s 228.671us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1564.722us 1 1 100.00
lc_ctrl_sec_cm 3.000s 228.671us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1564.722us 1 1 100.00
lc_ctrl_sec_cm 3.000s 228.671us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1564.722us 1 1 100.00
lc_ctrl_sec_cm 3.000s 228.671us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 1564.722us 1 1 100.00
lc_ctrl_sec_cm 3.000s 228.671us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 410.281us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 350.171us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 3911.808us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 240.599us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.000s 240.599us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 443.719us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 411.729us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 411.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 11.000s 17507.871us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 107865133772864809585899931253085272434710397241035141123793552153779567208740 1709
UVM_INFO @ 17507870726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---