| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
92.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| otbn_smoke | 17.000s | 795.335us | 1 | 1 | 100.00 | |
| otbn_smoke_vectorized | 7.000s | 93.557us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 216.648us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 4.000s | 23.672us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 4.000s | 75.032us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 6.000s | 57.435us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 7.000s | 39.080us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 7.000s | 63.029us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 4.000s | 75.032us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 7.000s | 39.080us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 100.000s | 2967.824us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 16.000s | 334.271us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 36.000s | 87.509us | 1 | 1 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 60.000s | 668.594us | 1 | 1 | 100.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 45.000s | 124.021us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 68.000s | 258.420us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 8.000s | 46.336us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 1 | 1 | 100.00 | |||
| otbn_zero_state_err_urnd | 9.000s | 20.347us | 1 | 1 | 100.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 16.000s | 331.166us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 5.000s | 28.449us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 4.000s | 13.308us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 4.000s | 114.135us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 4.000s | 114.135us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 4.000s | 23.672us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 4.000s | 75.032us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 7.000s | 39.080us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 50.195us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 4.000s | 23.672us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 4.000s | 75.032us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 7.000s | 39.080us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 50.195us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 14.000s | 52.065us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 42.801us | 1 | 1 | 100.00 | |
| internal_integrity | 2 | 4 | 50.00 | |||
| otbn_alu_bignum_mod_err | 8.000s | 109.598us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 10.000s | 56.855us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 9.000s | 91.182us | 0 | 1 | 0.00 | |
| otbn_urnd_err | 7.000s | 9.195us | 0 | 1 | 0.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 8.000s | 11.344us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 7.000s | 68.861us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 1 | 1 | 100.00 | |||
| otbn_partial_wipe | 6.000s | 61.831us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| otbn_tl_intg_err | 18.000s | 514.486us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 25.000s | 358.885us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 17.000s | 795.335us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 8.000s | 42.801us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 14.000s | 52.065us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 18.000s | 514.486us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 8.000s | 46.336us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 14.000s | 52.065us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 42.801us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 9.000s | 20.347us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 8.000s | 11.344us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 216.648us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 14.000s | 52.065us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 42.801us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 9.000s | 20.347us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 8.000s | 11.344us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 8.000s | 46.336us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 5 | 5 | 100.00 | |||
| otbn_imem_err | 14.000s | 52.065us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 8.000s | 42.801us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 9.000s | 20.347us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 8.000s | 11.344us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 216.648us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 6.000s | 92.774us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 8.000s | 16.668us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 23.000s | 205.410us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 23.000s | 205.410us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 11.000s | 546.346us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_bignum_intg_err | 7.000s | 39.139us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 9.000s | 22.433us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 9.000s | 22.433us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 10.000s | 47.709us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 216.648us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 216.648us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 216.648us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 45.000s | 124.021us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 216.648us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 216.648us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 8.000s | 16.205us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 10.000s | 216.648us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| otbn_sec_cm | 364.000s | 10938.935us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otbn_stress_all_with_rand_reset | 148.000s | 2667.918us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error | 1 test run | |||
| otbn_mac_bignum_acc_err | 3756141713380414475017843389038524113075330776091044939559932616100252204740 | 118 |
UVM_INFO @ 91181593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (otbn_base_vseq.sv:349) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) | 1 test run | |||
| otbn_stress_all_with_rand_reset | 34962045062777321888206805348555449274608656661877955176684786167155164474107 | 201 |
UVM_INFO @ 2667917869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed | 1 test run | |||
| otbn_urnd_err | 25710694357827215195738175687715759539300884847251228498891118072288755320340 | 113 |
UVM_ERROR @ 9194782 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 9194782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|