Simulation Results: otp_ctrl

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.91 %
  • code
  • 71.86 %
  • assert
  • 93.90 %
  • func
  • 52.97 %
  • line
  • 87.47 %
  • branch
  • 83.97 %
  • cond
  • 85.76 %
  • toggle
  • 64.13 %
  • FSM
  • 37.95 %
Validation stages
V1
88.89%
V2
65.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.690s 56.697us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.550s 364.553us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.030s 296.785us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.570s 60.343us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.890s 1707.402us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.360s 374.150us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.530s 87.741us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.570s 60.343us 1 1 100.00
otp_ctrl_csr_aliasing 5.360s 374.150us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.220s 81.447us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.930s 159.811us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 136.180s 15373.134us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.590s 120.798us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 12.690s 7693.433us 0 1 0.00
otp_ctrl_check_fail 13.870s 3811.810us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.580s 1802.862us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 44.060s 40666.937us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 17.040s 2088.568us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 10.610s 7004.694us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 17.990s 511.462us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 5.980s 615.588us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 19.140s 9148.430us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 8.860s 1332.546us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.730s 47.256us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.070s 112.442us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.170s 329.928us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.170s 329.928us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.030s 296.785us 1 1 100.00
otp_ctrl_csr_rw 1.570s 60.343us 1 1 100.00
otp_ctrl_csr_aliasing 5.360s 374.150us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.680s 215.423us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.030s 296.785us 1 1 100.00
otp_ctrl_csr_rw 1.570s 60.343us 1 1 100.00
otp_ctrl_csr_aliasing 5.360s 374.150us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.680s 215.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
otp_ctrl_tl_intg_err 18.380s 11463.722us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 18.380s 11463.722us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.550s 364.553us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.550s 364.553us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
otp_ctrl_macro_errs 5.980s 615.588us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
otp_ctrl_macro_errs 5.980s 615.588us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.950s 841.659us 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.590s 120.798us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 13.870s 3811.810us 1 1 100.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 44.060s 40666.937us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 44.060s 40666.937us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 44.060s 40666.937us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 44.060s 40666.937us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 44.060s 40666.937us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.550s 364.553us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 44.060s 40666.937us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.550s 364.553us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 297.750s 39397.387us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.580s 1802.862us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.550s 364.553us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.550s 364.553us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 5.980s 615.588us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 97.360s 62586.931us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 20.900s 886.591us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_background_chks 40249017137441717678753954975663047266553668772406692471644524404429284014669 6641
UVM_INFO @ 7693433114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 76400599964310740537831951139136265535781282033666287204354796831052975069515 17132
UVM_INFO @ 9148430147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35680980488914938291530336472051064654181749824918679102347585065849256589088 5202
UVM_INFO @ 886590692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 95932483010685428311971900427696721290940590977817443630352120000969136104630 2181
UVM_INFO @ 1332546239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 48798758443496101123518071354018998695616864987305270394862386731835284822214 110225
UVM_INFO @ 15373133745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 53792432263000011489799908163417352584679346418877268258060709191510197911958 95
UVM_INFO @ 62586930562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_dai_lock 15310768439578140917746007612053523193864969406465775454877768908047940435090 32439
UVM_INFO @ 40666936641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 12964719044492917661567753021843882326268714540911509942900648012505830268933 3073
UVM_INFO @ 615588459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_parallel_key_req 42116104860980767764115013166567788849801371419899936352070717718622939235576 17185
UVM_INFO @ 2088568197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:675) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 29089387491649479356181757318942999071837479803006484033809034352201849515882 103
UVM_INFO @ 87741214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---