Simulation Results: rom_ctrl/32kb

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.43 %
  • code
  • 81.00 %
  • assert
  • 97.09 %
  • func
  • 96.20 %
  • block
  • 81.27 %
  • line
  • 81.35 %
  • branch
  • 81.82 %
  • toggle
  • 84.65 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 771.277us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 57.098us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 81.813us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 136.812us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 58.832us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 107.473us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 81.813us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 58.832us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.000s 52.176us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.000s 51.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 164.348us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 7.000s 1411.446us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 737.657us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 108.313us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 3.000s 210.042us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 3.000s 210.042us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 57.098us 1 1 100.00
rom_ctrl_csr_rw 2.000s 81.813us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 58.832us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 63.077us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 57.098us 1 1 100.00
rom_ctrl_csr_rw 2.000s 81.813us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 58.832us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 63.077us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 1.554us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 6.000s 428.441us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 97.000s 6615.059us 1 1 100.00
rom_ctrl_tl_intg_err 11.000s 176.574us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 97.000s 6615.059us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 97.000s 6615.059us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 1.554us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 1.554us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 1.554us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 1.554us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 1.554us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 97.000s 6615.059us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 97.000s 6615.059us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 771.277us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 771.277us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 771.277us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 11.000s 176.574us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 1.554us 0 1 0.00
rom_ctrl_kmac_err_chk 3.000s 737.657us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 1.554us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 1.554us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 2.000s 1.554us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 6.000s 428.441us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 97.000s 6615.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 40.000s 6727.763us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 1219746468551569547235067860576151636111119583615925097070229255188222179094 88
UVM_INFO @ 164347558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:278) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 103405597932147191855945243341791377917440579212731758529116170356222915464542 87
UVM_INFO @ 1554279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---