Simulation Results: rom_ctrl/64kb

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.50 %
  • code
  • 80.91 %
  • assert
  • 96.65 %
  • func
  • 81.95 %
  • block
  • 81.18 %
  • line
  • 81.26 %
  • branch
  • 81.58 %
  • toggle
  • 84.61 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 402.500us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 86.247us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 87.260us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 154.610us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 116.379us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 53.663us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 87.260us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 116.379us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.000s 61.805us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 94.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 4.386us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.000s 1121.403us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.000s 739.944us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 55.139us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 3.000s 283.383us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 3.000s 283.383us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 86.247us 1 1 100.00
rom_ctrl_csr_rw 2.000s 87.260us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 116.379us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 119.592us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 86.247us 1 1 100.00
rom_ctrl_csr_rw 2.000s 87.260us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 116.379us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 119.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 399.000s 1000000.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 8.000s 2291.756us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 98.000s 317.847us 1 1 100.00
rom_ctrl_tl_intg_err 46.000s 323.012us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 98.000s 317.847us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 98.000s 317.847us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 399.000s 1000000.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 399.000s 1000000.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 399.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 399.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 399.000s 1000000.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 98.000s 317.847us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 98.000s 317.847us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 402.500us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 402.500us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 402.500us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 46.000s 323.012us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 399.000s 1000000.000us 0 1 0.00
rom_ctrl_kmac_err_chk 6.000s 739.944us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 399.000s 1000000.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 399.000s 1000000.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 399.000s 1000000.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 8.000s 2291.756us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 98.000s 317.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 4.000s 427.959us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 94393198205607555775845549631287432993185937353358758082374607366357346691730 88
UVM_INFO @ 4385736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rom_ctrl_corrupt_sig_fatal_chk 55425132509632511094105778641290428158463147472273367138871433637316729625972 88
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---