Simulation Results: rstmgr

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.64 %
  • code
  • 99.40 %
  • assert
  • 97.44 %
  • func
  • 93.07 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.98 %
  • toggle
  • 99.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.180s 69.307us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.330s 94.574us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.830s 36.337us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.900s 136.611us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.480s 54.363us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.730s 97.155us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.830s 36.337us 1 1 100.00
rstmgr_csr_aliasing 1.480s 54.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.030s 91.377us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.170s 45.412us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.980s 48.162us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.000s 685.557us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.000s 685.557us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.000s 685.557us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.000s 685.557us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 10.600s 1630.254us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.910s 46.193us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.650s 87.483us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.650s 87.483us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.330s 94.574us 1 1 100.00
rstmgr_csr_rw 0.830s 36.337us 1 1 100.00
rstmgr_csr_aliasing 1.480s 54.363us 1 1 100.00
rstmgr_same_csr_outstanding 0.940s 42.253us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.330s 94.574us 1 1 100.00
rstmgr_csr_rw 0.830s 36.337us 1 1 100.00
rstmgr_csr_aliasing 1.480s 54.363us 1 1 100.00
rstmgr_same_csr_outstanding 0.940s 42.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 15.920s 3458.803us 1 1 100.00
rstmgr_tl_intg_err 4.580s 624.659us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 15.920s 3458.803us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 15.920s 3458.803us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.580s 624.659us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.100s 65.151us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.210s 423.479us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.930s 292.876us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 15.920s 3458.803us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.830s 36.337us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.830s 36.337us 1 1 100.00