Simulation Results

Simulation Results: rv_dm/use_dmi_interface

12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.21 %

code
73.01 %

assert
96.59 %

func
92.02 %

block
89.19 %

line
88.96 %

branch
70.64 %

toggle
71.74 %

FSM
60.71 %

Validation stages

V1		92.59%
V2		69.57%
V2S		71.43%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	32.000s	1914.288us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	35.000s	170.164us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	31.000s	489.020us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	34.000s	8291.566us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	31.000s	800.903us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	37.000s	4716.035us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	34.000s	3256.305us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	48.000s	54368.127us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	59.000s	91868.471us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	295.655us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	30.000s	263.640us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	399.652us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	33.000s	424.947us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	31.000s	192.227us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	35.000s	329.429us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	33.000s	161.040us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	32.000s	751.943us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	295.655us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	32.000s	563.788us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	31.000s	1472.586us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	399.652us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	30.000s	19.717us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	32.000s	293.059us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	30.000s	107.941us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	49.000s	2162.828us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	46.000s	731.343us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	32.000s	97.334us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	46.000s	731.343us	1	1	100.00
	rv_dm_csr_rw	30.000s	107.941us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	30.000s	54.943us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	31.000s	50.445us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	32.000s	1914.288us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	30.000s	308.886us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	31.000s	267.341us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	30.000s	361.876us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	32.000s	1174.394us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	31.000s	1772.604us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	33.000s	339.039us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	33.000s	3585.710us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	34.000s	12593.535us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	30.000s	169.019us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	35.000s	2064.398us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	31.000s	600.616us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	29.000s	39.138us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	39.000s	6617.466us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	96.000s	4916.407us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	31.000s	133.932us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	37.000s	7163.416us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	77.083us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	32.000s	187.847us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	32.000s	187.847us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	46.000s	731.343us	1	1	100.00
	rv_dm_csr_hw_reset	32.000s	293.059us	1	1	100.00
	rv_dm_csr_rw	30.000s	107.941us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	718.300us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	46.000s	731.343us	1	1	100.00
	rv_dm_csr_hw_reset	32.000s	293.059us	1	1	100.00
	rv_dm_csr_rw	30.000s	107.941us	1	1	100.00
	rv_dm_same_csr_outstanding	34.000s	718.300us	1	1	100.00

V2S

5/7 passed

71.43 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	32.000s	1347.547us	1	1	100.00
	rv_dm_tl_intg_err	36.000s	1471.683us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	36.000s	1471.683us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	35.000s	2064.398us	1	1	100.00
	rv_dm_debug_disabled	30.000s	62.751us	0	1	0.00
sec_cm_lc_dft_en_intersig_mubi				1	2	50.00
	rv_dm_sba_debug_disabled	35.000s	2064.398us	1	1	100.00
	rv_dm_debug_disabled	30.000s	62.751us	0	1	0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	32.000s	1914.288us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				0	1	0.00
	rv_dm_buffered_enable	31.000s	275.347us	0	1	0.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	33.000s	166.923us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	33.000s	166.923us	1	1	100.00
sec_cm_exec_ctrl_mubi				0	1	0.00
	rv_dm_buffered_enable	31.000s	275.347us	0	1	0.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	36.000s	6612.068us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	151.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	81439906928074444450168227923974343546522282923716135023569561545431694475224	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23813
	rv_dm_autoincr_sba_tl_access	10614633733862378501430592697598144835056274501815204732326216877570190193949	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @16084
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	111398850176410715569627921263162140508576601498775560423668604523231193843264	107	UVM_INFO @ 339039467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	25136961655668880937995881920396642482332412725899319137055005055575860458403	107	UVM_INFO @ 3585710000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	4306471765579112258056586622893954391111652972749292000830143408456419610248	87	UVM_INFO @ 424946618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	24629916577757043686237054681846487372617823589394410013240414805551216113546	117	UVM_INFO @ 6612067894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	18488013998577484409383239017602659442574392953227442107249191407094542419079	87	UVM_INFO @ 169018802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	53327179077277804712980675842425469747335712863964553309881674526903100546222	91	UVM_INFO @ 7163416189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	98729526411259176290408580459828858908715843128763771337412661645986859943047	87	UVM_INFO @ 39137623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23865) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	82035955500035831571259970776107019408062055886916019059705878858761322539585	87	). UVM_INFO @ 19716976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)				1 test run
	rv_dm_debug_disabled	17146414973057240071715850991084306458608894252779921788864455867579401462816	89	UVM_INFO @ 62751228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				1 test run
	rv_dm_buffered_enable	94933676833382283238365327835986572158413264483402155563343272282964514173920	91	UVM_INFO @ 275347445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	22666419678000676953913759825393470805896864428990166970236382552790414012623	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---