Simulation Results: rv_timer

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.90 %
  • code
  • 90.45 %
  • assert
  • 98.10 %
  • func
  • 99.15 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 597.038us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 55.775us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 60.393us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 90.068us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 22.039us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 26.982us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 60.393us 1 1 100.00
rv_timer_csr_aliasing 1.000s 22.039us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.000s 133.749us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.000s 167.930us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 318.000s 357492.429us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 318.000s 357492.429us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.000s 10934.555us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 14.353us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 38.150us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 175.698us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 175.698us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 55.775us 1 1 100.00
rv_timer_csr_rw 1.000s 60.393us 1 1 100.00
rv_timer_csr_aliasing 1.000s 22.039us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 45.729us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 55.775us 1 1 100.00
rv_timer_csr_rw 1.000s 60.393us 1 1 100.00
rv_timer_csr_aliasing 1.000s 22.039us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 45.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 42.186us 1 1 100.00
rv_timer_tl_intg_err 2.000s 206.747us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 206.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 219.931us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 235.712us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 6.000s 881.560us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 49072413257754096899057376345750503765658503991446795274699103600938559529793 84
UVM_INFO @ 219931068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 9878166461758711271532303657194535367420746636279901884596042218073213037408 84
UVM_INFO @ 133749024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 45844516375986005698331889395347431252504362431505849325427833951429330604784 84
UVM_INFO @ 235712297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 64795557246567848947397461487264363064639623775539535938444778252125798809784 144
UVM_INFO @ 881559570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---