Simulation Results: spi_host

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.99 %
  • code
  • 91.14 %
  • assert
  • 96.60 %
  • func
  • 88.24 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 21.000s 3625.886us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 52.097us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 21.676us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 151.216us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 24.553us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 30.040us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 21.676us 1 1 100.00
spi_host_csr_aliasing 1.000s 24.553us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 23.618us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 21.052us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 120.905us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 254.922us 1 1 100.00
spi_host_error_cmd 1.000s 23.288us 1 1 100.00
spi_host_event 5.000s 2487.206us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 272.612us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 272.612us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 272.612us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 73.000s 3781.879us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 95.658us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 64.521us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 272.612us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 272.612us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 21.000s 3625.886us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 21.000s 3625.886us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 103.791us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 4918.125us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 17.000s 3031.221us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 191.111us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 254.922us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 39.846us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 115.760us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 505.090us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 505.090us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 52.097us 1 1 100.00
spi_host_csr_rw 2.000s 21.676us 1 1 100.00
spi_host_csr_aliasing 1.000s 24.553us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 25.194us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 52.097us 1 1 100.00
spi_host_csr_rw 2.000s 21.676us 1 1 100.00
spi_host_csr_aliasing 1.000s 24.553us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 25.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 713.447us 1 1 100.00
spi_host_sec_cm 2.000s 519.425us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 713.447us 1 1 100.00