Simulation Results: uart

 
12/08/2026 19:42:27 DVSim: v1.50.1 sha: c96e07a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.73 %
  • code
  • 73.64 %
  • assert
  • 98.85 %
  • func
  • 90.69 %
  • block
  • 98.58 %
  • line
  • 99.24 %
  • branch
  • 97.24 %
  • toggle
  • 73.08 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 4.000s 650.390us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 28.365us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 18.099us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 85.326us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 86.715us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 38.241us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 18.099us 1 1 100.00
uart_csr_aliasing 1.000s 86.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 31.000s 228086.631us 1 1 100.00
parity 2 2 100.00
uart_smoke 4.000s 650.390us 1 1 100.00
uart_tx_rx 31.000s 228086.631us 1 1 100.00
parity_error 2 2 100.00
uart_intr 488.000s 557513.374us 1 1 100.00
uart_rx_parity_err 145.000s 117515.178us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 31.000s 228086.631us 1 1 100.00
uart_intr 488.000s 557513.374us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 52.000s 93233.639us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 13.000s 123014.285us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 104.000s 85867.186us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 488.000s 557513.374us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 488.000s 557513.374us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 488.000s 557513.374us 1 1 100.00
perf 1 1 100.00
uart_perf 125.000s 40089.235us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 6.000s 3729.793us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 6.000s 3729.793us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 32.000s 23270.458us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.000s 3486.329us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 16.000s 6622.735us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 35.000s 6761.492us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 61.000s 37630.604us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 778.000s 302326.119us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 42.205us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 2.000s 18.563us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 3.000s 287.845us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 3.000s 287.845us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 28.365us 1 1 100.00
uart_csr_rw 1.000s 18.099us 1 1 100.00
uart_csr_aliasing 1.000s 86.715us 1 1 100.00
uart_same_csr_outstanding 1.000s 70.898us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 28.365us 1 1 100.00
uart_csr_rw 1.000s 18.099us 1 1 100.00
uart_csr_aliasing 1.000s 86.715us 1 1 100.00
uart_same_csr_outstanding 1.000s 70.898us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 243.548us 1 1 100.00
uart_tl_intg_err 1.000s 209.930us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 209.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 26.000s 8720.963us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 96208997745943788387678587508454984815289084145892018489533032495036167733232 84
UVM_ERROR @ 22567810180 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 22567820597 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 203 [0xcb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 22719242109 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 22719242109 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0