Simulation Results: aes/gcm_unmasked

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.22 %
  • code
  • 90.94 %
  • assert
  • 97.75 %
  • func
  • 60.96 %
  • block
  • 90.42 %
  • line
  • 92.28 %
  • branch
  • 82.69 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 137.533us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 69.215us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 350.383us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 80.344us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 1853.447us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 72.162us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 81.655us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 80.344us 1 1 100.00
aes_csr_aliasing 2.000s 72.162us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 69.215us 1 1 100.00
aes_config_error 2.000s 95.619us 1 1 100.00
aes_stress 3.000s 451.193us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 69.215us 1 1 100.00
aes_config_error 2.000s 95.619us 1 1 100.00
aes_stress 3.000s 451.193us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 451.193us 1 1 100.00
aes_b2b 3.000s 136.130us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 451.193us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 69.215us 1 1 100.00
aes_config_error 2.000s 95.619us 1 1 100.00
aes_stress 3.000s 451.193us 1 1 100.00
aes_alert_reset 2.000s 72.063us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 52.274us 1 1 100.00
aes_config_error 2.000s 95.619us 1 1 100.00
aes_alert_reset 2.000s 72.063us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 119.513us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 139.159us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 72.063us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 451.193us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 451.193us 1 1 100.00
aes_sideload 2.000s 158.243us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 131.903us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 2.000s 57.051us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 69.279us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 82.298us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 82.298us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 350.383us 1 1 100.00
aes_csr_rw 1.000s 80.344us 1 1 100.00
aes_csr_aliasing 2.000s 72.162us 1 1 100.00
aes_same_csr_outstanding 1.000s 93.299us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 350.383us 1 1 100.00
aes_csr_rw 1.000s 80.344us 1 1 100.00
aes_csr_aliasing 2.000s 72.162us 1 1 100.00
aes_same_csr_outstanding 1.000s 93.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 92.831us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 68.956us 0 1 0.00
aes_control_fi 2.000s 71.335us 1 1 100.00
aes_cipher_fi 2.000s 77.394us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 176.313us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 176.313us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 176.313us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 176.313us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 184.069us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 8.000s 2750.140us 1 1 100.00
aes_tl_intg_err 2.000s 85.718us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 85.718us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 72.063us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 176.313us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 176.313us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 69.215us 1 1 100.00
aes_stress 3.000s 451.193us 1 1 100.00
aes_alert_reset 2.000s 72.063us 1 1 100.00
aes_core_fi 17.000s 10009.458us 0 1 0.00
sec_cm_gcm_config_sparse 2 3 66.67
aes_config_error 2.000s 95.619us 1 1 100.00
aes_stress 3.000s 451.193us 1 1 100.00
aes_core_fi 17.000s 10009.458us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 176.313us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 85.790us 1 1 100.00
aes_stress 3.000s 451.193us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 451.193us 1 1 100.00
aes_sideload 2.000s 158.243us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 85.790us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 85.790us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 85.790us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 85.790us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 85.790us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 451.193us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 451.193us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 68.956us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 68.956us 0 1 0.00
aes_control_fi 2.000s 71.335us 1 1 100.00
aes_cipher_fi 2.000s 77.394us 1 1 100.00
aes_ctr_fi 1.000s 137.779us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 68.956us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 68.956us 0 1 0.00
aes_control_fi 2.000s 71.335us 1 1 100.00
aes_cipher_fi 2.000s 77.394us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 77.394us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 68.956us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 68.956us 0 1 0.00
aes_control_fi 2.000s 71.335us 1 1 100.00
aes_ctr_fi 1.000s 137.779us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 68.956us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 68.956us 0 1 0.00
aes_control_fi 2.000s 71.335us 1 1 100.00
aes_cipher_fi 2.000s 77.394us 1 1 100.00
aes_ctr_fi 1.000s 137.779us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 72.063us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 68.956us 0 1 0.00
aes_control_fi 2.000s 71.335us 1 1 100.00
aes_cipher_fi 2.000s 77.394us 1 1 100.00
aes_ctr_fi 1.000s 137.779us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 68.956us 0 1 0.00
aes_control_fi 2.000s 71.335us 1 1 100.00
aes_cipher_fi 2.000s 77.394us 1 1 100.00
aes_ctr_fi 1.000s 137.779us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 68.956us 0 1 0.00
aes_control_fi 2.000s 71.335us 1 1 100.00
aes_ctr_fi 1.000s 137.779us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 68.956us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 68.956us 0 1 0.00
aes_control_fi 2.000s 71.335us 1 1 100.00
aes_cipher_fi 2.000s 77.394us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 14.357us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 94983724741757750533537159953067584095534503793829325662718587609110236815461 2794
UVM_INFO @ 92830621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 47608292838715689934165694184649288614660802084421042855092277340103643080941 985
UVM_INFO @ 57050978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 51378585800977092082713013040375688804507347495264584129696507143869617971697 4860
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 4885029711833014852267408330955672241154643015123509158891164028102933569064 150
UVM_INFO @ 10009457955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 46402807376505313290619052788938507126361551677724992293518499419297093255185 140
UVM_INFO @ 14357089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---