Simulation Results: clkmgr

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.23 %
  • code
  • 68.17 %
  • assert
  • 88.43 %
  • func
  • 72.09 %
  • line
  • 81.46 %
  • branch
  • 86.53 %
  • cond
  • 75.67 %
  • toggle
  • 97.17 %
  • FSM
  • 0.00 %
Validation stages
V1
83.33%
V2
76.92%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.190s 23.818us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.970s 17.633us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.080s 65.834us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 7.820s 875.522us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.220s 61.994us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.820s 18.449us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.080s 65.834us 1 1 100.00
clkmgr_csr_aliasing 1.220s 61.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.120s 61.946us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.860s 24.581us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.880s 15.294us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.190s 23.818us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.740s 10.172us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.680s 5.484us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.740s 10.172us 0 1 0.00
stress_all 1 1 100.00
clkmgr_stress_all 1.170s 54.809us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.880s 19.201us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.610s 148.353us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.610s 148.353us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 0.970s 17.633us 1 1 100.00
clkmgr_csr_rw 1.080s 65.834us 1 1 100.00
clkmgr_csr_aliasing 1.220s 61.994us 1 1 100.00
clkmgr_same_csr_outstanding 0.750s 4.408us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 0.970s 17.633us 1 1 100.00
clkmgr_csr_rw 1.080s 65.834us 1 1 100.00
clkmgr_csr_aliasing 1.220s 61.994us 1 1 100.00
clkmgr_same_csr_outstanding 0.750s 4.408us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.930s 147.977us 0 1 0.00
clkmgr_tl_intg_err 1.060s 49.188us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 62.323us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 62.323us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 62.323us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 62.323us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.630s 5.086us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.060s 49.188us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.740s 10.172us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.680s 5.484us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 62.323us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.370s 91.508us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.080s 65.834us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.930s 147.977us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.080s 65.834us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.080s 65.834us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.930s 147.977us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.840s 7.102us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.700s 5.773us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 32053418160033944205945975987005792179506188041810578301325926262502288997155 84
UVM_INFO @ 5483832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 65570549962403017912890029681809550373051131065384022762269229112174742712043 85
UVM_INFO @ 5773275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 68479270338349455046329005588448698193832147627561849767621464907235549776327 82
UVM_INFO @ 10172178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 49827068359226724333529440121375880735856990471519555599583624474077554604422 80
UVM_INFO @ 7101711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 48579217637168246244604557550141615520113644038330318704880637060660031353288 81
UVM_INFO @ 5085660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 9049490836591994806314574066758928630112103453576903432525503588684860421773 140
UVM_INFO @ 147977213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_tl_intg_err 48626760738364542665566672793318897070484153733445407036916099663785217000427 111
UVM_INFO @ 49188465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 14282119545122340919671989905305965041597453236795899391911176067598739103560 81
UVM_INFO @ 875521716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 49251753281967535105934936133020695387455288323115236733700070860563455124828 81
UVM_INFO @ 4408039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---