Simulation Results: csrng

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.02 %
  • code
  • 92.22 %
  • assert
  • 93.23 %
  • func
  • 75.62 %
  • block
  • 96.89 %
  • line
  • 97.59 %
  • branch
  • 92.26 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 27.263us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 52.146us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 27.692us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 18.000s 562.621us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 150.144us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 83.359us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 27.692us 1 1 100.00
csrng_csr_aliasing 4.000s 150.144us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
alerts 1 1 100.00
csrng_alert 13.000s 321.184us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 39.131us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 39.131us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 468.000s 32706.831us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 26.715us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 61.346us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 63.707us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 63.707us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 52.146us 1 1 100.00
csrng_csr_rw 2.000s 27.692us 1 1 100.00
csrng_csr_aliasing 4.000s 150.144us 1 1 100.00
csrng_same_csr_outstanding 3.000s 84.911us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 52.146us 1 1 100.00
csrng_csr_rw 2.000s 27.692us 1 1 100.00
csrng_csr_aliasing 4.000s 150.144us 1 1 100.00
csrng_same_csr_outstanding 3.000s 84.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 7.000s 941.103us 1 1 100.00
csrng_tl_intg_err 3.000s 117.694us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 33.703us 1 1 100.00
csrng_csr_rw 2.000s 27.692us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 13.000s 321.184us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 468.000s 32706.831us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
csrng_sec_cm 7.000s 941.103us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
csrng_sec_cm 7.000s 941.103us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
csrng_sec_cm 7.000s 941.103us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
csrng_sec_cm 7.000s 941.103us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
csrng_sec_cm 7.000s 941.103us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 13.000s 321.184us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 468.000s 32706.831us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 13.000s 321.184us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 117.694us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
csrng_sec_cm 7.000s 941.103us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
csrng_sec_cm 7.000s 941.103us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 120.743us 1 1 100.00
csrng_err 2.000s 24.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.123s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:667) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 65689677357442451448089535780349048266392287053190383433235757122789920345369 100
UVM_INFO @ 39130820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 11814856233943222468235590941092663270821894370750106532947013476320878922890 None