Simulation Results: dma

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.73 %
  • code
  • 90.41 %
  • assert
  • 96.50 %
  • func
  • 64.29 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 456.187us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 1980.869us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 334.384us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 23.719us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 17.756us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 1679.635us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 246.613us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 201.165us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 17.756us 1 1 100.00
dma_csr_aliasing 4.000s 246.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 37.000s 16214.715us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 275.000s 125709.970us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 213.000s 83804.753us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 213.000s 83804.753us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 275.000s 125709.970us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 246.000s 26346.035us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 213.000s 83804.753us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 11.000s 1079.848us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 137.000s 14603.869us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 29.605us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 17.026us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 1.000s 64.493us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 1.000s 64.493us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 23.719us 1 1 100.00
dma_csr_rw 1.000s 17.756us 1 1 100.00
dma_csr_aliasing 4.000s 246.613us 1 1 100.00
dma_same_csr_outstanding 2.000s 645.879us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 23.719us 1 1 100.00
dma_csr_rw 1.000s 17.756us 1 1 100.00
dma_csr_aliasing 4.000s 246.613us 1 1 100.00
dma_same_csr_outstanding 2.000s 645.879us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 19.000s 386.619us 1 1 100.00
dma_generic_stress 246.000s 26346.035us 1 1 100.00
dma_handshake_stress 213.000s 83804.753us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 2784.109us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 102.653us 1 1 100.00
dma_sec_cm 1.000s 53.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 97.000s 6245.839us 1 1 100.00
dma_longer_transfer 5.000s 189.305us 1 1 100.00
dma_stress_all_with_rand_reset 12.000s 1510.800us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 94218220679825220477532259454950437713476687633040952654698146148941029322288 120
UVM_INFO @ 1510799546ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---