Simulation Results: edn/edn0

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 78.52 %
  • code
  • 87.96 %
  • assert
  • 96.68 %
  • func
  • 50.91 %
  • block
  • 94.90 %
  • line
  • 97.56 %
  • branch
  • 88.97 %
  • toggle
  • 76.94 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 17.842us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 46.723us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 39.789us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 6.000s 319.381us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 20.578us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 31.955us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 39.789us 1 1 100.00
edn_csr_aliasing 2.000s 20.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.000s 105.366us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.000s 105.366us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.000s 105.366us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 24.077us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 31.261us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 37.146us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 12.741us 1 1 100.00
edn_disable_auto_req_mode 2.000s 25.248us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 6.000s 329.047us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 29.351us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 14.010us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 181.521us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 181.521us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 46.723us 1 1 100.00
edn_csr_rw 2.000s 39.789us 1 1 100.00
edn_csr_aliasing 2.000s 20.578us 1 1 100.00
edn_same_csr_outstanding 2.000s 25.574us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 46.723us 1 1 100.00
edn_csr_rw 2.000s 39.789us 1 1 100.00
edn_csr_aliasing 2.000s 20.578us 1 1 100.00
edn_same_csr_outstanding 2.000s 25.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 8.000s 3709.742us 1 1 100.00
edn_tl_intg_err 2.000s 89.212us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 27.271us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 31.261us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.000s 3709.742us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 8.000s 3709.742us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 8.000s 3709.742us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 8.000s 3709.742us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 31.261us 1 1 100.00
edn_sec_cm 8.000s 3709.742us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 31.261us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 89.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 56.000s 11473.028us 1 1 100.00