Simulation Results: entropy_src/rng_16bits

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 69.44 %
  • code
  • 82.53 %
  • assert
  • 74.20 %
  • func
  • 51.58 %
  • block
  • 94.15 %
  • line
  • 97.80 %
  • branch
  • 86.18 %
  • toggle
  • 52.41 %
  • FSM
  • 93.75 %
Validation stages
V1
83.33%
V2
93.75%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 84.380us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 102.988us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 60.674us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 5.000s 121.011us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 5.000s 358.278us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 12.394us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 60.674us 1 1 100.00
entropy_src_csr_aliasing 5.000s 358.278us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 84.380us 1 1 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
entropy_src_fw_ov 101.000s 14112.784us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 101.000s 14112.784us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 440.000s 14066.689us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
entropy_src_intr 16.000s 1029.016us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
entropy_src_functional_alerts 5.000s 177.559us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 88.000s 14524.907us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 42.638us 1 1 100.00
firmware_ov_read_contiguous_data 0 1 0.00
entropy_src_fw_ov_contiguous 2.000s 46.539us 0 1 0.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 70.703us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 19.200us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 739.021us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 739.021us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 102.988us 1 1 100.00
entropy_src_csr_rw 1.000s 60.674us 1 1 100.00
entropy_src_csr_aliasing 5.000s 358.278us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 82.836us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 102.988us 1 1 100.00
entropy_src_csr_rw 1.000s 60.674us 1 1 100.00
entropy_src_csr_aliasing 5.000s 358.278us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 82.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 95.328us 1 1 100.00
entropy_src_tl_intg_err 3.000s 119.376us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
entropy_src_cfg_regwen 1.000s 39.178us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
entropy_src_fw_ov 101.000s 14112.784us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 42.638us 1 1 100.00
entropy_src_sec_cm 3.000s 95.328us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 42.638us 1 1 100.00
entropy_src_sec_cm 3.000s 95.328us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 172.000s 14166.673us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 42.638us 1 1 100.00
entropy_src_sec_cm 3.000s 95.328us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 42.638us 1 1 100.00
entropy_src_sec_cm 3.000s 95.328us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 42.638us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 177.559us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 119.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 62.000s 13060.158us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 8.000s 646.414us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 8532716098230174660124327048368695026630815617997881069274848579104773057273 118
UVM_INFO @ 646413868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_scoreboard.sv:2128) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.observe_fifo_depth 1 test run
entropy_src_fw_ov_contiguous 71438733994492360597248054841787974872170090531530946198557326215849185868430 159
UVM_INFO @ 46538981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 77039939699122159213472687250061346255991019920393153410065026739425151491522 113
UVM_INFO @ 12393720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---