Simulation Results: hmac

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.08 %
  • code
  • 96.08 %
  • assert
  • 97.17 %
  • func
  • 28.99 %
  • block
  • 97.64 %
  • line
  • 98.44 %
  • branch
  • 94.11 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.000s 2482.793us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 17.968us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 221.116us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.000s 13041.312us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 420.541us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 20.515us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 221.116us 1 1 100.00
hmac_csr_aliasing 3.000s 420.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 52.000s 4856.850us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 53.000s 1521.085us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 209.000s 26559.195us 1 1 100.00
hmac_test_sha384_vectors 25.000s 318.373us 1 1 100.00
hmac_test_sha512_vectors 26.000s 330.772us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 1125.871us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 455.914us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 326.925us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 23.000s 10340.198us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 29.000s 12573.802us 1 1 100.00
error 1 1 100.00
hmac_error 96.000s 2983.263us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 89.000s 9405.231us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.000s 2482.793us 1 1 100.00
hmac_long_msg 52.000s 4856.850us 1 1 100.00
hmac_back_pressure 53.000s 1521.085us 1 1 100.00
hmac_datapath_stress 29.000s 12573.802us 1 1 100.00
hmac_burst_wr 23.000s 10340.198us 1 1 100.00
hmac_stress_all 215.000s 7548.875us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.000s 2482.793us 1 1 100.00
hmac_long_msg 52.000s 4856.850us 1 1 100.00
hmac_back_pressure 53.000s 1521.085us 1 1 100.00
hmac_datapath_stress 29.000s 12573.802us 1 1 100.00
hmac_wipe_secret 89.000s 9405.231us 1 1 100.00
hmac_test_sha256_vectors 209.000s 26559.195us 1 1 100.00
hmac_test_sha384_vectors 25.000s 318.373us 1 1 100.00
hmac_test_sha512_vectors 26.000s 330.772us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 1125.871us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 455.914us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 326.925us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.000s 2482.793us 1 1 100.00
hmac_long_msg 52.000s 4856.850us 1 1 100.00
hmac_back_pressure 53.000s 1521.085us 1 1 100.00
hmac_datapath_stress 29.000s 12573.802us 1 1 100.00
hmac_burst_wr 23.000s 10340.198us 1 1 100.00
hmac_error 96.000s 2983.263us 1 1 100.00
hmac_wipe_secret 89.000s 9405.231us 1 1 100.00
hmac_test_sha256_vectors 209.000s 26559.195us 1 1 100.00
hmac_test_sha384_vectors 25.000s 318.373us 1 1 100.00
hmac_test_sha512_vectors 26.000s 330.772us 1 1 100.00
hmac_test_hmac256_vectors 11.000s 1125.871us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 455.914us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 326.925us 1 1 100.00
hmac_stress_all 215.000s 7548.875us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 215.000s 7548.875us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 41.678us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 15.999us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 228.658us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 228.658us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 17.968us 1 1 100.00
hmac_csr_rw 2.000s 221.116us 1 1 100.00
hmac_csr_aliasing 3.000s 420.541us 1 1 100.00
hmac_same_csr_outstanding 3.000s 182.237us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 17.968us 1 1 100.00
hmac_csr_rw 2.000s 221.116us 1 1 100.00
hmac_csr_aliasing 3.000s 420.541us 1 1 100.00
hmac_same_csr_outstanding 3.000s 182.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 109.053us 1 1 100.00
hmac_tl_intg_err 2.000s 101.596us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 101.596us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.000s 2482.793us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 76.286us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 184.000s 5783.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 47.318us 1 1 100.00