Simulation Results

Simulation Results: i2c

13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.51 %

code
85.63 %

assert
96.19 %

func
80.72 %

block
95.92 %

line
95.31 %

branch
92.68 %

toggle
72.52 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		82.93%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	185.000s	8532.921us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	13.000s	845.831us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	28.976us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	51.104us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	2682.204us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	3.000s	410.267us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	82.713us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	51.104us	1	1	100.00
	i2c_csr_aliasing	3.000s	410.267us	1	1	100.00

34/41 passed

82.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	58.449us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	57.000s	21906.214us	0	1	0.00
host_maxperf				0	1	0.00
	i2c_host_perf	3601.000s	0.000us	0	1	0.00
host_override				1	1	100.00
	i2c_host_override	2.000s	67.052us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	2734.000s	13121.031us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1671.000s	2005.189us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	634.186us	1	1	100.00
	i2c_host_fifo_fmt_empty	50.000s	1421.786us	1	1	100.00
	i2c_host_fifo_reset_rx	7.000s	453.956us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	979.000s	3999.231us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	9.000s	3830.534us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	84.957us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	1910.384us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	34.000s	69935.320us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	6.000s	1645.502us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	12.000s	1053.927us	1	1	100.00
	i2c_target_intr_smoke	5.000s	1005.555us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	590.503us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	156.773us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	12.000s	1053.927us	1	1	100.00
	i2c_target_intr_stress_wr	3601.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.000s	8244.822us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1848.000s	5497.565us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.000s	4814.509us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.000s	269.771us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	374.555us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	193.772us	1	1	100.00
host_mode_config_perf				1	2	50.00
	i2c_host_perf	3601.000s	0.000us	0	1	0.00
	i2c_host_perf_precise	2.000s	92.740us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	9.000s	3830.534us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	5.000s	342.738us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	490.504us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	2092.104us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	152.964us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.000s	243.531us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	3098.192us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	95.978us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	101.186us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	102.318us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	102.318us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	28.976us	1	1	100.00
	i2c_csr_rw	1.000s	51.104us	1	1	100.00
	i2c_csr_aliasing	3.000s	410.267us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	23.365us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	28.976us	1	1	100.00
	i2c_csr_rw	1.000s	51.104us	1	1	100.00
	i2c_csr_aliasing	3.000s	410.267us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	23.365us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	169.549us	1	1	100.00
	i2c_sec_cm	2.000s	79.107us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	169.549us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	11.000s	4618.479us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	67.210us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	6.000s	470.540us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_perf	113864639550979402552577062321503237605051286564681493953187204218975784755490	None
	i2c_target_stress_wr	45544443920935052371423511846090813872900746427609066997394878065878603449984	None
	i2c_target_intr_stress_wr	28895532559767180714563841670635121560066919973669059248884471092583456894330	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	111388900355323531295886232914654657415443361085421217419722125425092019672948	97	UVM_INFO @ 58449223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	18324731370333759354325265195829133105654857971152330166974518381590893853775	121	UVM_INFO @ 21906214369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	42741452132427628834199068995963878729520065083719358011924498854839654937234	101	UVM_INFO @ 470540242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	33967709313880366725356183784093977105083979581028620115820290826329961279256	93	UVM_INFO @ 1910383505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1382) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	56473182997738295121528634471069235017135583060787876127174677726587095832683	87	UVM_INFO @ 67210254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	61611498541123678415645124392424083450568478172213929479455707800877410656026	96	UVM_INFO @ 4618479145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	88712712298186211579579602609520583576513619380325353670977080000301609821028	96	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------