Simulation Results: lc_ctrl/volatile_unlock_disabled

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.97 %
  • code
  • 92.61 %
  • assert
  • 96.54 %
  • func
  • 86.77 %
  • block
  • 96.61 %
  • line
  • 97.29 %
  • branch
  • 91.38 %
  • toggle
  • 86.52 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 51.226us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 17.754us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 32.160us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.000s 129.080us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.237us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 36.514us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 32.160us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 2024.838us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 368.447us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.109us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 52.384us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 3297.474us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.000s 245.414us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 3297.474us 1 1 100.00
lc_ctrl_prog_failure 2.000s 52.384us 1 1 100.00
lc_ctrl_errors 3.000s 245.414us 1 1 100.00
lc_ctrl_security_escalation 5.000s 333.204us 1 1 100.00
lc_ctrl_jtag_state_failure 20.000s 5543.649us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 405.959us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 5106.773us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 1311.570us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1036.530us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 405.959us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 5106.773us 1 1 100.00
lc_ctrl_jtag_access 5.000s 1691.002us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 1809.316us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 62.930us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 214.674us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.000s 2851.991us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 1079.167us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 24.103us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.000s 131.624us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 65.466us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.000s 345.757us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 23.768us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 20.000s 7289.993us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 40.552us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 48.285us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 48.285us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 17.754us 1 1 100.00
lc_ctrl_csr_rw 1.000s 32.160us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.237us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 44.167us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 17.754us 1 1 100.00
lc_ctrl_csr_rw 1.000s 32.160us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 36.237us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 44.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 266.562us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 394.352us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 394.352us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 368.447us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 3297.474us 1 1 100.00
lc_ctrl_sec_cm 3.000s 266.562us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 3297.474us 1 1 100.00
lc_ctrl_sec_cm 3.000s 266.562us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 3297.474us 1 1 100.00
lc_ctrl_sec_cm 3.000s 266.562us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 3297.474us 1 1 100.00
lc_ctrl_sec_cm 3.000s 266.562us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 3297.474us 1 1 100.00
lc_ctrl_sec_cm 3.000s 266.562us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 3297.474us 1 1 100.00
lc_ctrl_sec_cm 3.000s 266.562us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 3297.474us 1 1 100.00
lc_ctrl_sec_cm 3.000s 266.562us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 3297.474us 1 1 100.00
lc_ctrl_sec_cm 3.000s 266.562us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 333.204us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 2024.838us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1036.530us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 463.692us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 463.692us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 7217.582us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1502.113us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1502.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 28.000s 8824.235us 1 1 100.00