Simulation Results: lc_ctrl/volatile_unlock_enabled

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.01 %
  • code
  • 93.11 %
  • assert
  • 96.69 %
  • func
  • 83.23 %
  • block
  • 97.11 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 86.84 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 72.213us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 17.553us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 218.736us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 113.101us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 37.897us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 36.915us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 218.736us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 37.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 1034.488us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 212.694us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 40.565us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 56.606us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 2689.122us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 3134.079us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 2689.122us 1 1 100.00
lc_ctrl_prog_failure 3.000s 56.606us 1 1 100.00
lc_ctrl_errors 5.000s 3134.079us 1 1 100.00
lc_ctrl_security_escalation 4.000s 2421.314us 1 1 100.00
lc_ctrl_jtag_state_failure 9.000s 5899.860us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.000s 633.753us 1 1 100.00
lc_ctrl_jtag_errors 12.000s 3789.636us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 7518.617us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1148.074us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.000s 633.753us 1 1 100.00
lc_ctrl_jtag_errors 12.000s 3789.636us 1 1 100.00
lc_ctrl_jtag_access 2.000s 148.322us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.000s 1579.438us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 356.165us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 1299.302us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.000s 2067.973us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 884.587us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 49.654us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 100.046us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 41.701us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 299.146us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 43.375us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 45.000s 29176.379us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 47.284us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 126.110us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 126.110us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.553us 1 1 100.00
lc_ctrl_csr_rw 2.000s 218.736us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 37.897us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 29.927us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.553us 1 1 100.00
lc_ctrl_csr_rw 2.000s 218.736us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 37.897us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 29.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 2052.377us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 194.055us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 194.055us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 212.694us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 2689.122us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2052.377us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 2689.122us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2052.377us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 2689.122us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2052.377us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 2689.122us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2052.377us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 2689.122us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2052.377us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 2689.122us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2052.377us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 2689.122us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2052.377us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 2689.122us 1 1 100.00
lc_ctrl_sec_cm 3.000s 2052.377us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 2421.314us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 1034.488us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 1148.074us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 2206.533us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 2206.533us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 1148.625us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 242.208us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 242.208us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.000s 1634.803us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 72209812387047874440197215126297911960795907291431409813573171128378266115943 164
UVM_INFO @ 1634802588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---