Simulation Results: mbx

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.60 %
  • code
  • 86.10 %
  • assert
  • 97.24 %
  • func
  • 76.46 %
  • block
  • 94.21 %
  • line
  • 94.30 %
  • branch
  • 84.32 %
  • toggle
  • 79.67 %
Validation stages
V1
83.33%
V2
63.64%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 64.000s 11943.507us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 50.795us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 27.517us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 6.000s 740.633us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 14.948us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 57.830us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 27.517us 1 1 100.00
mbx_csr_aliasing 2.000s 14.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 3.000s 610.494us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 3.000s 136.506us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 1.000s 27.809us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 8.000s 3024.581us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 22.279us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 82.650us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 9.632us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 9.632us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 50.795us 1 1 100.00
mbx_csr_rw 1.000s 27.517us 1 1 100.00
mbx_csr_aliasing 2.000s 14.948us 1 1 100.00
mbx_same_csr_outstanding 2.000s 62.244us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 50.795us 1 1 100.00
mbx_csr_rw 1.000s 27.517us 1 1 100.00
mbx_csr_aliasing 2.000s 14.948us 1 1 100.00
mbx_same_csr_outstanding 2.000s 62.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 78.063us 1 1 100.00
mbx_sec_cm 1.000s 41.102us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 2 test runs
mbx_stress_zero_delays 18309041405283912835016621349171623653368156169172508312795332329313608079677 300
UVM_INFO @ 136505961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_imbx_oob 61432630075808035841343149769698351240655205943715855298511000604256629141777 91
UVM_INFO @ 27809168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:625) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 86744345673128824568202731228354114525917328033509754966655601263969198598757 85
TL item was: req: (cip_tl_seq_item@18156) { a_addr: 'h25d36270 a_data: 'h29d22d83 a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'h9c a_opcode: 'h1 a_user: 'h256f3 d_param: 'h0 d_source: 'h9c d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 9632287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 90870185225874165440999151818185745304096319246634168652218460785139714712226 92
TL item was: req: (cip_tl_seq_item@23139) { a_addr: 'h355cb650 a_data: 'h8497e5ac a_mask: 'h0 a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h1 a_user: 'h243c3 d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 57830003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed 1 test run
mbx_stress 26736540533953232759363430291568082031209208671833781728512651055511183832426 195
UVM_ERROR @ 610493663 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 610493663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---