Simulation Results: otbn

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.56 %
  • code
  • 81.85 %
  • assert
  • 89.80 %
  • func
  • 97.03 %
  • block
  • 97.74 %
  • line
  • 97.95 %
  • branch
  • 81.89 %
  • toggle
  • 81.36 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 9.000s 76.757us 1 1 100.00
otbn_smoke_vectorized 7.000s 62.610us 1 1 100.00
single_binary 1 1 100.00
otbn_single 15.000s 144.500us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 27.418us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 18.102us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 8.000s 87.737us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 17.694us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 71.106us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 18.102us 1 1 100.00
otbn_csr_aliasing 4.000s 17.694us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 131.000s 22307.224us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 25.000s 2365.858us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 32.000s 173.105us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 58.000s 739.295us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 27.000s 104.911us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 19.000s 114.908us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 43.742us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 42.065us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 13.000s 53.207us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 38.358us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 32.728us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 187.878us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 187.878us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 27.418us 1 1 100.00
otbn_csr_rw 5.000s 18.102us 1 1 100.00
otbn_csr_aliasing 4.000s 17.694us 1 1 100.00
otbn_same_csr_outstanding 5.000s 60.791us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 27.418us 1 1 100.00
otbn_csr_rw 5.000s 18.102us 1 1 100.00
otbn_csr_aliasing 4.000s 17.694us 1 1 100.00
otbn_same_csr_outstanding 5.000s 60.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 41.409us 1 1 100.00
otbn_dmem_err 13.000s 27.645us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 9.000s 29.232us 1 1 100.00
otbn_controller_ispr_rdata_err 7.000s 51.491us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 53.473us 1 1 100.00
otbn_urnd_err 5.000s 22.779us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 17.652us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 72.633us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 74.016us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
otbn_tl_intg_err 12.000s 143.866us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 69.000s 291.651us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 76.757us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 13.000s 27.645us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 41.409us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 12.000s 143.866us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 43.742us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 41.409us 1 1 100.00
otbn_dmem_err 13.000s 27.645us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 42.065us 1 1 100.00
otbn_illegal_mem_acc 5.000s 17.652us 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 15.000s 144.500us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 41.409us 1 1 100.00
otbn_dmem_err 13.000s 27.645us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 42.065us 1 1 100.00
otbn_illegal_mem_acc 5.000s 17.652us 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 43.742us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 41.409us 1 1 100.00
otbn_dmem_err 13.000s 27.645us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 42.065us 1 1 100.00
otbn_illegal_mem_acc 5.000s 17.652us 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 15.000s 144.500us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 61.318us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 34.203us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 30.000s 173.807us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 30.000s 173.807us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 31.215us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 402.437us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 50.302us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 50.302us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 9.946us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 15.000s 144.500us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 15.000s 144.500us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 15.000s 144.500us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 27.000s 104.911us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 15.000s 144.500us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 15.000s 144.500us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 55.409us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 15.000s 144.500us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 365.000s 14982.419us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 80.000s 806.089us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 77631785737042654730388138973242078803366016836998845228811180794940636478809 159
UVM_INFO @ 806088737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---