Simulation Results: otp_ctrl

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.30 %
  • code
  • 72.17 %
  • assert
  • 93.99 %
  • func
  • 53.73 %
  • line
  • 87.37 %
  • branch
  • 84.12 %
  • cond
  • 85.87 %
  • toggle
  • 66.19 %
  • FSM
  • 37.30 %
Validation stages
V1
100.00%
V2
70.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.900s 60.905us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 8.210s 376.196us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.730s 128.754us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.320s 47.229us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.090s 1199.105us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 6.420s 285.357us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.880s 425.059us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.320s 47.229us 1 1 100.00
otp_ctrl_csr_aliasing 6.420s 285.357us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.570s 45.746us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.430s 43.863us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 105.440s 2903.732us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.580s 340.118us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 10.910s 2654.315us 1 1 100.00
otp_ctrl_check_fail 8.220s 689.337us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 8.800s 2852.651us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 8.860s 1593.980us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 1.980s 135.978us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 13.290s 1778.849us 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 31.590s 2922.387us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 6.360s 2929.339us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 2.560s 99.318us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 6.410s 497.565us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.470s 57.130us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.100s 816.570us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.240s 193.963us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.240s 193.963us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.730s 128.754us 1 1 100.00
otp_ctrl_csr_rw 2.320s 47.229us 1 1 100.00
otp_ctrl_csr_aliasing 6.420s 285.357us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.790s 110.826us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.730s 128.754us 1 1 100.00
otp_ctrl_csr_rw 2.320s 47.229us 1 1 100.00
otp_ctrl_csr_aliasing 6.420s 285.357us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.790s 110.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
otp_ctrl_tl_intg_err 20.300s 2833.538us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 20.300s 2833.538us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 8.210s 376.196us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 8.210s 376.196us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
otp_ctrl_macro_errs 6.360s 2929.339us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
otp_ctrl_macro_errs 6.360s 2929.339us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.450s 855.571us 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.580s 340.118us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 8.220s 689.337us 1 1 100.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 8.860s 1593.980us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 8.860s 1593.980us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 8.860s 1593.980us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 8.860s 1593.980us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 8.860s 1593.980us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 8.210s 376.196us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 8.860s 1593.980us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 8.210s 376.196us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 316.360s 58164.617us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 8.800s 2852.651us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 8.210s 376.196us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 8.210s 376.196us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 6.360s 2929.339us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 86.160s 26644.870us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 20.380s 464.162us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_dai_lock 82003348183935559946557777195744581710683910382618210393563746733444727730713 6787
UVM_INFO @ 1593980120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 82477589482001992392578261130505073155586939115758158708861649453306995350087 214
UVM_INFO @ 135977630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 32063628004098230276150328835161776214339875289977071486814350731769867858725 594
UVM_INFO @ 99317830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53999142507245165653018894337362763821418959013296968357071579588330098350272 20596
UVM_INFO @ 464161790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_partition_walk 78517098902891646058285034547596347256830227539752031727602728855365886469141 160061
UVM_INFO @ 2903731936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 82461664402769170607078886383362936147968789845762452045112760209716762906372 95
UVM_INFO @ 26644870082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 80841296217538482739514138772955672064691286186226746707136175607664350247786 6261
UVM_INFO @ 2929339081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:961) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_stress_all 6665493377198789605023321675534583367225888828319738777325191032191127696373 5485
UVM_INFO @ 497565134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---