Simulation Results: rstmgr

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.25 %
  • code
  • 99.22 %
  • assert
  • 98.53 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.75 %
  • toggle
  • 99.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.430s 57.975us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.220s 93.635us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.880s 36.124us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.110s 58.884us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.800s 52.671us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.530s 96.598us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.880s 36.124us 1 1 100.00
rstmgr_csr_aliasing 1.800s 52.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.980s 85.348us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.910s 39.866us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.400s 59.180us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.600s 614.272us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.600s 614.272us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.600s 614.272us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.600s 614.272us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 46.860s 7461.282us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.990s 38.765us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.920s 67.008us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.920s 67.008us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.220s 93.635us 1 1 100.00
rstmgr_csr_rw 0.880s 36.124us 1 1 100.00
rstmgr_csr_aliasing 1.800s 52.671us 1 1 100.00
rstmgr_same_csr_outstanding 0.910s 36.586us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.220s 93.635us 1 1 100.00
rstmgr_csr_rw 0.880s 36.124us 1 1 100.00
rstmgr_csr_aliasing 1.800s 52.671us 1 1 100.00
rstmgr_same_csr_outstanding 0.910s 36.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 16.180s 3445.964us 1 1 100.00
rstmgr_tl_intg_err 2.810s 330.318us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 16.180s 3445.964us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 16.180s 3445.964us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.810s 330.318us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.110s 69.647us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.510s 476.687us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.240s 291.414us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 16.180s 3445.964us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.880s 36.124us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.880s 36.124us 1 1 100.00