Simulation Results

Simulation Results: rv_dm/use_dmi_interface

13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.85 %

code
81.56 %

assert
96.74 %

func
88.25 %

block
92.46 %

line
93.05 %

branch
79.51 %

toggle
73.31 %

FSM
80.36 %

Validation stages

V1		92.59%
V2		73.91%
V2S		100.00%
V3		0.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	33.000s	1077.877us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	30.000s	150.939us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	29.000s	622.823us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	39.000s	25827.368us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	30.000s	217.646us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	42.000s	5477.902us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	32.000s	1339.785us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	53.000s	19217.627us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	78.000s	47230.508us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	35.000s	1457.452us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	35.000s	124.160us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	189.893us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	29.000s	173.028us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	31.000s	156.946us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	32.000s	503.771us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	31.000s	110.462us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	40.000s	186.490us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	35.000s	1457.452us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	31.000s	166.027us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	32.000s	1234.023us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	189.893us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	30.000s	25.569us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	31.000s	431.328us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	31.000s	147.754us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	48.000s	1110.354us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	64.000s	15846.973us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	30.000s	235.074us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	64.000s	15846.973us	1	1	100.00
	rv_dm_csr_rw	31.000s	147.754us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	30.000s	56.092us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	32.000s	49.425us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	33.000s	1077.877us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	30.000s	240.080us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	30.000s	786.878us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	31.000s	175.097us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	32.000s	378.953us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	36.000s	4115.511us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	30.000s	345.572us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	32.000s	156.062us	0	1	0.00
sba_autoincrement				1	1	100.00
	rv_dm_autoincr_sba_tl_access	34.000s	6031.587us	1	1	100.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	30.000s	609.387us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	32.000s	1448.171us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	35.000s	911.560us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	30.000s	48.403us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	44.000s	9889.986us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	46.000s	7833.438us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	31.000s	254.404us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	29.000s	88.474us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	31.000s	128.606us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	693.767us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	693.767us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	64.000s	15846.973us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	431.328us	1	1	100.00
	rv_dm_csr_rw	31.000s	147.754us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	257.890us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	64.000s	15846.973us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	431.328us	1	1	100.00
	rv_dm_csr_rw	31.000s	147.754us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	257.890us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	30.000s	1547.013us	1	1	100.00
	rv_dm_tl_intg_err	40.000s	2471.332us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	40.000s	2471.332us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	1448.171us	1	1	100.00
	rv_dm_debug_disabled	30.000s	74.620us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	1448.171us	1	1	100.00
	rv_dm_debug_disabled	30.000s	74.620us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	33.000s	1077.877us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	32.000s	286.036us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	79.687us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	79.687us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	32.000s	286.036us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	32.000s	449.595us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	472.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	103980016666412773249440284673880250157430935513168672680865837326368951925595	107	UVM_INFO @ 345571915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	72519513885850459572052008838583266119684814831772105431341688633967188085514	107	UVM_INFO @ 156062355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	70921580689905970418334569695316950891978678167549209256754735359352099450825	87	UVM_INFO @ 173027595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	96184027942427695045993941374123612118506881683828611653836843301835051205218	92	UVM_INFO @ 449594628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	10240303480835538042409091589402022782684802119635271990026903960247234693374	87	UVM_INFO @ 609387419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	107167783127743172038974184666561961169527812164936647520725229732493632451654	88	UVM_INFO @ 88473585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared:				1 test run
	rv_dm_sba_tl_access	45044945648517117273459706769914432450926704790538165479936527341997797033641	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23817
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	22860629265856586771258192722855837055609430504572069271431407230911957214136	87	UVM_INFO @ 48403258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23858) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	61933794408861119701367720405878292128604491255155478654235395600464709364835	87	). UVM_INFO @ 25569283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	112455295231348678535827749743306083531752523525759850571863990186435595618665	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---