Simulation Results: rv_timer

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 90.45 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 172.406us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 22.177us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 17.098us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 459.016us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 70.215us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 15.619us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 17.098us 1 1 100.00
rv_timer_csr_aliasing 1.000s 70.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 3.000s 1101.300us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 426.534us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 2.000s 613.648us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 2.000s 613.648us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.000s 1449.851us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 16.927us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 19.076us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 300.798us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 300.798us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 22.177us 1 1 100.00
rv_timer_csr_rw 1.000s 17.098us 1 1 100.00
rv_timer_csr_aliasing 1.000s 70.215us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 54.102us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 22.177us 1 1 100.00
rv_timer_csr_rw 1.000s 17.098us 1 1 100.00
rv_timer_csr_aliasing 1.000s 70.215us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 54.102us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 2.000s 130.509us 1 1 100.00
rv_timer_tl_intg_err 1.000s 153.414us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 153.414us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 1.000s 19.559us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 1.000s 176.718us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 13.000s 3908.164us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 101376902423203514188429266027855278102762459453615396783294416425751320014779 85
UVM_INFO @ 176718234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---