Simulation Results: spi_device/1r1w

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.05 %
  • code
  • 88.70 %
  • assert
  • 95.27 %
  • func
  • 74.16 %
  • block
  • 98.33 %
  • line
  • 98.65 %
  • branch
  • 96.96 %
  • toggle
  • 72.75 %
  • FSM
  • 86.46 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 457.000s 184809.573us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.000s 44.247us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 27.274us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 31.000s 27857.475us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 13.000s 673.107us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 196.711us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 27.274us 1 1 100.00
spi_device_csr_aliasing 13.000s 673.107us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 19.204us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 91.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 34.432us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 8.005us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 12.023us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 3.000s 93.799us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 3.000s 93.799us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 7.000s 1648.232us 1 1 100.00
spi_device_tpm_sts_read 2.000s 112.878us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 19.000s 1109.577us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.000s 38.022us 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 31.000s 15459.243us 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 31.000s 15459.243us 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 7.000s 1360.870us 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 7.000s 1360.870us 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 7.000s 1360.870us 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 7.000s 1360.870us 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 7.000s 1360.870us 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 14.000s 1018.872us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 16.000s 2209.383us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 16.000s 2209.383us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 16.000s 2209.383us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 9.000s 499.076us 1 1 100.00
spi_device_read_buffer_direct 15.000s 1194.618us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 16.000s 2209.383us 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 56.000s 5360.840us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 516.794us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 516.794us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 39.000s 7643.202us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 457.000s 184809.573us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 59.000s 5960.826us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 2.000s 39.348us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 17.932us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 32.437us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 7.000s 202.251us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 7.000s 202.251us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 44.247us 1 1 100.00
spi_device_csr_rw 2.000s 27.274us 1 1 100.00
spi_device_csr_aliasing 13.000s 673.107us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 800.969us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 44.247us 1 1 100.00
spi_device_csr_rw 2.000s 27.274us 1 1 100.00
spi_device_csr_aliasing 13.000s 673.107us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 800.969us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 197.097us 1 1 100.00
spi_device_tl_intg_err 17.000s 657.094us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 17.000s 657.094us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 73050396232923154417165188815950600625422753042304329388639641512289220454594 87
UVM_ERROR @ 4484940 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905] not found within the scope .
UVM_ERROR @ 4484940 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 361302528659533223837663225902431225676653467130913532049929750585700053490 85
UVM_ERROR @ 9585514 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x362 [1101100010] vs 0x0 [0])
UVM_ERROR @ 9647514 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3c2 [1111000010] vs 0x0 [0])
UVM_ERROR @ 9662514 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x209 [1000001001] vs 0x0 [0])
UVM_ERROR @ 9727514 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3e6 [1111100110] vs 0x0 [0])