Simulation Results: spi_host

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.60 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 11.000s 2323.573us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 50.563us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 28.809us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 146.046us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 97.887us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 23.249us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 28.809us 1 1 100.00
spi_host_csr_aliasing 2.000s 97.887us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.252us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 48.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 29.156us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 72.883us 1 1 100.00
spi_host_error_cmd 1.000s 27.708us 1 1 100.00
spi_host_event 26.000s 1365.816us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 48.217us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 48.217us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 48.217us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 27.000s 2313.294us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 14.000s 520.740us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 530.650us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 48.217us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 48.217us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 11.000s 2323.573us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 11.000s 2323.573us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 188.385us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 1414.234us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 19.000s 779.215us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 133.842us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 72.883us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 135.260us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 48.798us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 31.640us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 31.640us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 50.563us 1 1 100.00
spi_host_csr_rw 1.000s 28.809us 1 1 100.00
spi_host_csr_aliasing 2.000s 97.887us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 34.054us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 50.563us 1 1 100.00
spi_host_csr_rw 1.000s 28.809us 1 1 100.00
spi_host_csr_aliasing 2.000s 97.887us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 34.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 163.473us 1 1 100.00
spi_host_sec_cm 1.000s 70.752us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 163.473us 1 1 100.00