Simulation Results: sram_ctrl/main

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.10 %
  • code
  • 95.67 %
  • assert
  • 97.42 %
  • func
  • 92.20 %
  • block
  • 96.09 %
  • line
  • 96.75 %
  • branch
  • 94.32 %
  • toggle
  • 91.60 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 373.091us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 37.202us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.942us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 4.000s 1792.000us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 156.751us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 1432.885us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 52.942us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 156.751us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 91.000s 3022.149us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 52.000s 2868.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 25.000s 12236.114us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 138.000s 19519.270us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 152.000s 63169.952us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 19.000s 4876.347us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 38.000s 50015.816us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 49.000s 51971.885us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 1462.718us 1 1 100.00
sram_ctrl_partial_access_b2b 237.000s 36275.779us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 691.238us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.000s 1398.383us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 4476.302us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 1834.214us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 711.180us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 391.000s 65985.205us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 40.320us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 82.581us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 82.581us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 37.202us 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.942us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 156.751us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 30.212us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 37.202us 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.942us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 156.751us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 30.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 73723.631us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 722.273us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 90.776us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 722.273us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 90.776us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 1834.214us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 1834.214us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.942us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 49.000s 51971.885us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 49.000s 51971.885us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 49.000s 51971.885us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 38.000s 50015.816us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 1277.964us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 73723.631us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 724.478us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 373.091us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 373.091us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 49.000s 51971.885us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 722.273us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 38.000s 50015.816us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 722.273us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 722.273us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 373.091us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 722.273us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.000s 1011.530us 1 1 100.00