Simulation Results: sram_ctrl/ret

 
13/08/2026 20:41:30 DVSim: v1.50.1 sha: e58679d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.09 %
  • code
  • 82.40 %
  • assert
  • 98.08 %
  • func
  • 92.80 %
  • block
  • 93.89 %
  • line
  • 94.98 %
  • branch
  • 89.64 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 353.847us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 30.655us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.368us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 122.001us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 35.919us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 26.654us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 11.368us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 35.919us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 710.166us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 236.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 380.976us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 111.000s 5015.710us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 318.878us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 21.000s 1750.165us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 501.212us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 787.078us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 165.911us 1 1 100.00
sram_ctrl_partial_access_b2b 187.000s 11161.490us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 39.637us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 75.679us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 46.581us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 5.000s 358.207us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 71.129us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 27.000s 986.759us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 67.281us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 62.645us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 62.645us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 30.655us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.368us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 35.919us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 32.359us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 30.655us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.368us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 35.919us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 32.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 2068.645us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 619.222us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 128.532us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 619.222us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 128.532us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 358.207us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 358.207us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.368us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 787.078us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 787.078us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 787.078us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 501.212us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 36.432us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 2068.645us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 335.511us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 353.847us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 353.847us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 787.078us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 619.222us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 501.212us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 619.222us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 619.222us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 353.847us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 619.222us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 20.000s 4487.748us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 26282178969187437346636722439270717060526038115484038559498678843816853228902 92
UVM_INFO @ 26654116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---