| V1 |
|
100.00% |
| V2 |
|
95.45% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| uart_smoke | 3.000s | 6079.350us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| uart_csr_hw_reset | 1.000s | 45.088us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| uart_csr_rw | 2.000s | 17.168us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| uart_csr_bit_bash | 3.000s | 318.061us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| uart_csr_aliasing | 1.000s | 79.496us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_csr_mem_rw_with_rand_reset | 1.000s | 63.709us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| uart_csr_rw | 2.000s | 17.168us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 1.000s | 79.496us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| base_random_seq | 1 | 1 | 100.00 | |||
| uart_tx_rx | 24.000s | 24180.730us | 1 | 1 | 100.00 | |
| parity | 2 | 2 | 100.00 | |||
| uart_smoke | 3.000s | 6079.350us | 1 | 1 | 100.00 | |
| uart_tx_rx | 24.000s | 24180.730us | 1 | 1 | 100.00 | |
| parity_error | 2 | 2 | 100.00 | |||
| uart_intr | 20.000s | 158197.877us | 1 | 1 | 100.00 | |
| uart_rx_parity_err | 44.000s | 210347.941us | 1 | 1 | 100.00 | |
| watermark | 2 | 2 | 100.00 | |||
| uart_tx_rx | 24.000s | 24180.730us | 1 | 1 | 100.00 | |
| uart_intr | 20.000s | 158197.877us | 1 | 1 | 100.00 | |
| fifo_full | 1 | 1 | 100.00 | |||
| uart_fifo_full | 52.000s | 74324.018us | 1 | 1 | 100.00 | |
| fifo_overflow | 1 | 1 | 100.00 | |||
| uart_fifo_overflow | 65.000s | 76549.940us | 1 | 1 | 100.00 | |
| fifo_reset | 1 | 1 | 100.00 | |||
| uart_fifo_reset | 20.000s | 13687.323us | 1 | 1 | 100.00 | |
| rx_frame_err | 1 | 1 | 100.00 | |||
| uart_intr | 20.000s | 158197.877us | 1 | 1 | 100.00 | |
| rx_break_err | 1 | 1 | 100.00 | |||
| uart_intr | 20.000s | 158197.877us | 1 | 1 | 100.00 | |
| rx_timeout | 1 | 1 | 100.00 | |||
| uart_intr | 20.000s | 158197.877us | 1 | 1 | 100.00 | |
| perf | 1 | 1 | 100.00 | |||
| uart_perf | 455.000s | 24295.425us | 1 | 1 | 100.00 | |
| sys_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 5.000s | 2394.977us | 1 | 1 | 100.00 | |
| line_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 5.000s | 2394.977us | 1 | 1 | 100.00 | |
| rx_noise_filter | 0 | 1 | 0.00 | |||
| uart_noise_filter | 2.000s | 2314.200us | 0 | 1 | 0.00 | |
| rx_start_bit_filter | 1 | 1 | 100.00 | |||
| uart_rx_start_bit_filter | 4.000s | 2477.665us | 1 | 1 | 100.00 | |
| tx_overide | 1 | 1 | 100.00 | |||
| uart_tx_ovrd | 3.000s | 1278.849us | 1 | 1 | 100.00 | |
| rx_oversample | 1 | 1 | 100.00 | |||
| uart_rx_oversample | 4.000s | 4883.668us | 1 | 1 | 100.00 | |
| long_b2b_transfer | 1 | 1 | 100.00 | |||
| uart_long_xfer_wo_dly | 291.000s | 132204.590us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| uart_stress_all | 72.000s | 90527.931us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| uart_alert_test | 1.000s | 12.763us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| uart_intr_test | 1.000s | 16.974us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 2.000s | 217.911us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 2.000s | 217.911us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| uart_csr_hw_reset | 1.000s | 45.088us | 1 | 1 | 100.00 | |
| uart_csr_rw | 2.000s | 17.168us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 1.000s | 79.496us | 1 | 1 | 100.00 | |
| uart_same_csr_outstanding | 1.000s | 22.757us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| uart_csr_hw_reset | 1.000s | 45.088us | 1 | 1 | 100.00 | |
| uart_csr_rw | 2.000s | 17.168us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 1.000s | 79.496us | 1 | 1 | 100.00 | |
| uart_same_csr_outstanding | 1.000s | 22.757us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| uart_sec_cm | 1.000s | 75.879us | 1 | 1 | 100.00 | |
| uart_tl_intg_err | 2.000s | 88.008us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| uart_tl_intg_err | 2.000s | 88.008us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_stress_all_with_rand_reset | 22.000s | 2810.460us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uart_scoreboard.sv:499) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * | 1 test run | |||
| uart_noise_filter | 57134767372834581460919914722626393931904174237801940877685637292449126300107 | 83 |
UVM_ERROR @ 704353702 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 704645371 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 704728705 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 704812039 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 252 [0xfc]) reg name: uart_reg_block.rdata
|
|