Simulation Results: ac_range_check

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.63 %
  • code
  • 92.52 %
  • assert
  • 97.75 %
  • func
  • 57.61 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 79.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 27.000s 5630.519us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 29.000s 698.076us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 20.018us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 475.292us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 21.000s 2809.638us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 20.000s 1466.568us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 54.397us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 475.292us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 1466.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 24.470us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 22.000s 2257.933us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 125.000s 6579.857us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 15.365us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 15.900us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 97.765us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 97.765us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 20.018us 1 1 100.00
ac_range_check_csr_rw 2.000s 475.292us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 1466.568us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 54.122us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 20.018us 1 1 100.00
ac_range_check_csr_rw 2.000s 475.292us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 1466.568us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 54.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 1171.686us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 1171.686us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 1171.686us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 1171.686us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 88.000s 5281.299us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 13.907us 1 1 100.00
ac_range_check_tl_intg_err 5.000s 116.118us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 240.000s 2772.406us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 24.000s 1325.215us 1 1 100.00