Simulation Results: aes/gcm_unmasked

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.84 %
  • code
  • 90.50 %
  • assert
  • 97.75 %
  • func
  • 63.27 %
  • block
  • 90.51 %
  • line
  • 92.44 %
  • branch
  • 82.93 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 63.927us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 71.024us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 128.927us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 76.988us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 887.467us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 129.923us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 82.699us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 76.988us 1 1 100.00
aes_csr_aliasing 2.000s 129.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 71.024us 1 1 100.00
aes_config_error 2.000s 78.309us 1 1 100.00
aes_stress 2.000s 80.946us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 71.024us 1 1 100.00
aes_config_error 2.000s 78.309us 1 1 100.00
aes_stress 2.000s 80.946us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 80.946us 1 1 100.00
aes_b2b 4.000s 193.332us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 80.946us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 71.024us 1 1 100.00
aes_config_error 2.000s 78.309us 1 1 100.00
aes_stress 2.000s 80.946us 1 1 100.00
aes_alert_reset 2.000s 122.080us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 59.739us 1 1 100.00
aes_config_error 2.000s 78.309us 1 1 100.00
aes_alert_reset 2.000s 122.080us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 59.219us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 1007.017us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 122.080us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 80.946us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 80.946us 1 1 100.00
aes_sideload 2.000s 355.101us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 82.019us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 5.000s 270.735us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 84.310us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 79.222us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 79.222us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 128.927us 1 1 100.00
aes_csr_rw 1.000s 76.988us 1 1 100.00
aes_csr_aliasing 2.000s 129.923us 1 1 100.00
aes_same_csr_outstanding 2.000s 140.835us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 128.927us 1 1 100.00
aes_csr_rw 1.000s 76.988us 1 1 100.00
aes_csr_aliasing 2.000s 129.923us 1 1 100.00
aes_same_csr_outstanding 2.000s 140.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 145.356us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 1273.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 78.905us 1 1 100.00
aes_cipher_fi 2.000s 49.602us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 182.151us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 182.151us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 182.151us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 182.151us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 206.888us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 842.698us 1 1 100.00
aes_tl_intg_err 2.000s 201.389us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 201.389us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 122.080us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 182.151us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 182.151us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 71.024us 1 1 100.00
aes_stress 2.000s 80.946us 1 1 100.00
aes_alert_reset 2.000s 122.080us 1 1 100.00
aes_core_fi 2.000s 156.539us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 78.309us 1 1 100.00
aes_stress 2.000s 80.946us 1 1 100.00
aes_core_fi 2.000s 156.539us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 182.151us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 67.872us 1 1 100.00
aes_stress 2.000s 80.946us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 80.946us 1 1 100.00
aes_sideload 2.000s 355.101us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 67.872us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 67.872us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 67.872us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 67.872us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 67.872us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 80.946us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 80.946us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 1273.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 1273.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 78.905us 1 1 100.00
aes_cipher_fi 2.000s 49.602us 1 1 100.00
aes_ctr_fi 2.000s 74.594us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 1273.000s 200000.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 1273.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 78.905us 1 1 100.00
aes_cipher_fi 2.000s 49.602us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 49.602us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 1273.000s 200000.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 1273.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 78.905us 1 1 100.00
aes_ctr_fi 2.000s 74.594us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 1273.000s 200000.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 1273.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 78.905us 1 1 100.00
aes_cipher_fi 2.000s 49.602us 1 1 100.00
aes_ctr_fi 2.000s 74.594us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 122.080us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 1273.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 78.905us 1 1 100.00
aes_cipher_fi 2.000s 49.602us 1 1 100.00
aes_ctr_fi 2.000s 74.594us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 1273.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 78.905us 1 1 100.00
aes_cipher_fi 2.000s 49.602us 1 1 100.00
aes_ctr_fi 2.000s 74.594us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 1273.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 78.905us 1 1 100.00
aes_ctr_fi 2.000s 74.594us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 1273.000s 200000.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 1273.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 78.905us 1 1 100.00
aes_cipher_fi 2.000s 49.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 6.509us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_fi 102197204037579932126021182177056414182327573290472869962653023096110366634130 15998652
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 75600711549384320122266235142992202075367690915715246318271389317527082947577 28692
UVM_INFO @ 270734944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 41678887555516611123291600250091921128653524322082989587163880463730634791669 177
UVM_INFO @ 6509342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---