Simulation Results: alert_handler

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.85 %
  • code
  • 89.68 %
  • assert
  • 98.20 %
  • func
  • 75.66 %
  • line
  • 99.70 %
  • branch
  • 98.54 %
  • cond
  • 91.95 %
  • toggle
  • 82.38 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 15.880s 220.838us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 7.850s 139.429us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.110s 247.198us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 107.700s 5124.835us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 103.890s 1261.556us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 7.840s 276.246us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.110s 247.198us 1 1 100.00
alert_handler_csr_aliasing 103.890s 1261.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 72.950s 7746.360us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 29.310s 1075.804us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1469.410s 69515.377us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 56.980s 6144.546us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 15.880s 220.838us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 9.510s 568.977us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 26.020s 481.303us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 167.420s 52074.734us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 938.800s 55692.974us 1 1 100.00
alert_handler_lpg_stub_clk 969.220s 56576.272us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 210.040s 22644.607us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 7.600s 407.734us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 4.380s 276.273us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.430s 11.406us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.880s 67.128us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.880s 67.128us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 7.850s 139.429us 1 1 100.00
alert_handler_csr_rw 4.110s 247.198us 1 1 100.00
alert_handler_csr_aliasing 103.890s 1261.556us 1 1 100.00
alert_handler_same_csr_outstanding 9.350s 103.499us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 7.850s 139.429us 1 1 100.00
alert_handler_csr_rw 4.110s 247.198us 1 1 100.00
alert_handler_csr_aliasing 103.890s 1261.556us 1 1 100.00
alert_handler_same_csr_outstanding 9.350s 103.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 303.130s 6460.903us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 303.130s 6460.903us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 303.130s 6460.903us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 303.130s 6460.903us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 451.180s 10035.871us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 11.230s 249.880us 1 1 100.00
alert_handler_tl_intg_err 34.950s 2840.847us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 34.950s 2840.847us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 303.130s 6460.903us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 15.880s 220.838us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 15.880s 220.838us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 15.880s 220.838us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 15.880s 220.838us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 56.980s 6144.546us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 938.800s 55692.974us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 56.980s 6144.546us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1469.410s 69515.377us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1469.410s 69515.377us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 11.230s 249.880us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 11.230s 249.880us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 11.230s 249.880us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 11.230s 249.880us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 11.230s 249.880us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 11.230s 249.880us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 11.230s 249.880us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 11.230s 249.880us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 11.230s 249.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 209.440s 17502.623us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 76740276365059792090723901104073483469219121282094340471770964711667882656145 123
UVM_INFO @ 52074733955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 89910327380090080453478323864713775328187092572336814369305135542468957779090 170
UVM_INFO @ 407733867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 95259648338924304735300821183776268740092138001389721490938229102281423900590 231
UVM_INFO @ 17502622721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---