Simulation Results: clkmgr

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.81 %
  • code
  • 68.17 %
  • assert
  • 88.43 %
  • func
  • 55.83 %
  • line
  • 81.71 %
  • branch
  • 86.53 %
  • cond
  • 78.76 %
  • toggle
  • 93.87 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.650s 115.512us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.910s 37.726us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.800s 10.938us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.080s 117.677us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.760s 11.133us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.650s 3.477us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.800s 10.938us 0 1 0.00
clkmgr_csr_aliasing 0.760s 11.133us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.970s 42.061us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.560s 123.258us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.900s 13.229us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.650s 115.512us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.820s 22.432us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.670s 5.685us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.820s 22.432us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.750s 12.389us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.920s 38.317us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 4.000s 314.152us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 4.000s 314.152us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.910s 37.726us 1 1 100.00
clkmgr_csr_rw 0.800s 10.938us 0 1 0.00
clkmgr_csr_aliasing 0.760s 11.133us 0 1 0.00
clkmgr_same_csr_outstanding 0.830s 14.483us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.910s 37.726us 1 1 100.00
clkmgr_csr_rw 0.800s 10.938us 0 1 0.00
clkmgr_csr_aliasing 0.760s 11.133us 0 1 0.00
clkmgr_same_csr_outstanding 0.830s 14.483us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 93.180s 10145.852us 0 1 0.00
clkmgr_tl_intg_err 0.680s 3.311us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.420s 99.639us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.420s 99.639us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.420s 99.639us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.420s 99.639us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.710s 3.802us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.680s 3.311us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.820s 22.432us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.670s 5.685us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.420s 99.639us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 2.270s 214.410us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.800s 10.938us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 93.180s 10145.852us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.800s 10.938us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.800s 10.938us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 93.180s 10145.852us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.640s 7.598us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.840s 13.160us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 4 test runs
clkmgr_tl_intg_err 74827658284417743942706230530302898337019000754147863987056785050721601279697 88
UVM_INFO @ 3310728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 20770530132109590536506168082113886923219232462037802841604819727633675846077 82
UVM_INFO @ 10938403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 22506631232629560011015535752058897296082312160130359292006116617551418355431 81
UVM_INFO @ 11133051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 59822256118207038092691290280268613894995642614755037063165141986509871828529 82
UVM_INFO @ 3477197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 5033899253355972230083664261050184776213061400350407123300105879157246616924 82
UVM_INFO @ 22432325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 85666826447524929062679659489560301563654255898597369948593220258396527800585 84
UVM_INFO @ 13159820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 60018056573684284293606279278929259048057381909978789295183872397363191756897 84
UVM_INFO @ 5684905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 46764198853340132368009545222603995999306518007761036816155476460013694761652 84
UVM_INFO @ 12389164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 95071840471480123996541043463547357376230118652984765883160972904885167025737 80
UVM_INFO @ 7597733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 115326207949621353793810492684219594414688249551994484864130585493370681796772 81
UVM_INFO @ 3801554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1087) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 74590735506226404859941642494488164203741311739015445305928747024402723411589 171
UVM_INFO @ 10145851557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 94678889169819473776706345402247077091455651188356648654071973749501741029427 81
UVM_INFO @ 117677006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 33306489020729456860335238383485787701736629336126179568679894326131878587934 81
UVM_INFO @ 14482668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---