Simulation Results: dma

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.31 %
  • code
  • 90.73 %
  • assert
  • 95.97 %
  • func
  • 63.24 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 270.895us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 500.916us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 3506.830us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 24.378us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 464.735us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 3228.746us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 345.139us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 28.899us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 464.735us 1 1 100.00
dma_csr_aliasing 3.000s 345.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 81.000s 27118.688us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 100.000s 21022.075us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 645.000s 314049.192us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 645.000s 314049.192us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 100.000s 21022.075us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 297.000s 194601.658us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 645.000s 314049.192us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 11.000s 7814.226us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 126.000s 12880.970us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 14.246us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 22.479us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 492.608us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 492.608us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 24.378us 1 1 100.00
dma_csr_rw 2.000s 464.735us 1 1 100.00
dma_csr_aliasing 3.000s 345.139us 1 1 100.00
dma_same_csr_outstanding 2.000s 217.488us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 24.378us 1 1 100.00
dma_csr_rw 2.000s 464.735us 1 1 100.00
dma_csr_aliasing 3.000s 345.139us 1 1 100.00
dma_same_csr_outstanding 2.000s 217.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 21.000s 410.028us 1 1 100.00
dma_generic_stress 297.000s 194601.658us 1 1 100.00
dma_handshake_stress 645.000s 314049.192us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 9.000s 350.579us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 133.097us 1 1 100.00
dma_sec_cm 1.000s 12.635us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 85.000s 19812.674us 1 1 100.00
dma_longer_transfer 42.000s 7329.504us 1 1 100.00
dma_stress_all_with_rand_reset 4.000s 596.098us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 51879479701347382465585230857866623958088477660399524263659495119247574723266 100
UVM_INFO @ 596097848ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---