Simulation Results: edn/edn0

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 76.10 %
  • code
  • 83.26 %
  • assert
  • 95.80 %
  • func
  • 49.23 %
  • block
  • 94.12 %
  • line
  • 96.88 %
  • branch
  • 87.33 %
  • toggle
  • 68.20 %
  • FSM
  • 80.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 30.915us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 48.988us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 19.422us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 84.136us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 3.000s 72.448us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 90.627us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 19.422us 1 1 100.00
edn_csr_aliasing 3.000s 72.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 95.059us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 95.059us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 95.059us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 115.583us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 24.775us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 57.295us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 19.474us 1 1 100.00
edn_disable_auto_req_mode 2.000s 99.366us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 4.000s 403.455us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 27.411us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 50.380us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 53.988us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 53.988us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 48.988us 1 1 100.00
edn_csr_rw 1.000s 19.422us 1 1 100.00
edn_csr_aliasing 3.000s 72.448us 1 1 100.00
edn_same_csr_outstanding 1.000s 66.073us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 48.988us 1 1 100.00
edn_csr_rw 1.000s 19.422us 1 1 100.00
edn_csr_aliasing 3.000s 72.448us 1 1 100.00
edn_same_csr_outstanding 1.000s 66.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.000s 259.159us 1 1 100.00
edn_tl_intg_err 2.000s 90.924us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 27.912us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 24.775us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 259.159us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 259.159us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 259.159us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 259.159us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 24.775us 1 1 100.00
edn_sec_cm 4.000s 259.159us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 24.775us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 90.924us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 35.000s 2207.816us 1 1 100.00