Simulation Results: edn/edn1

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.11 %
  • code
  • 83.74 %
  • assert
  • 98.18 %
  • func
  • 79.41 %
  • line
  • 98.25 %
  • branch
  • 93.51 %
  • cond
  • 89.31 %
  • toggle
  • 95.57 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.790s 54.420us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 38.265us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 24.703us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.670s 49.758us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.900s 78.729us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.110s 35.163us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 24.703us 1 1 100.00
edn_csr_aliasing 0.900s 78.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.840s 93.005us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.840s 93.005us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.840s 93.005us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.690s 48.253us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.330s 82.870us 1 1 100.00
errs 1 1 100.00
edn_err 0.850s 36.118us 1 1 100.00
disable 2 2 100.00
edn_disable 0.750s 42.260us 1 1 100.00
edn_disable_auto_req_mode 0.960s 55.346us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.270s 294.570us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.770s 17.175us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.860s 20.769us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.780s 277.696us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.780s 277.696us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 38.265us 1 1 100.00
edn_csr_rw 0.750s 24.703us 1 1 100.00
edn_csr_aliasing 0.900s 78.729us 1 1 100.00
edn_same_csr_outstanding 1.390s 255.975us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 38.265us 1 1 100.00
edn_csr_rw 0.750s 24.703us 1 1 100.00
edn_csr_aliasing 0.900s 78.729us 1 1 100.00
edn_same_csr_outstanding 1.390s 255.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.920s 651.185us 1 1 100.00
edn_tl_intg_err 1.280s 58.843us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.940s 55.682us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.330s 82.870us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.920s 651.185us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.920s 651.185us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.920s 651.185us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.920s 651.185us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.330s 82.870us 1 1 100.00
edn_sec_cm 2.920s 651.185us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.330s 82.870us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.280s 58.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 41.540s 10179.203us 1 1 100.00