Simulation Results: entropy_src/rng_16bits

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 68.51 %
  • code
  • 81.15 %
  • assert
  • 73.92 %
  • func
  • 50.45 %
  • block
  • 93.93 %
  • line
  • 97.55 %
  • branch
  • 85.79 %
  • toggle
  • 52.70 %
  • FSM
  • 88.54 %
Validation stages
V1
83.33%
V2
93.75%
V2S
85.71%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 29.050us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 74.150us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 18.231us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 6.000s 459.670us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 194.553us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 26.194us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 18.231us 1 1 100.00
entropy_src_csr_aliasing 3.000s 194.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 2.000s 29.050us 1 1 100.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
entropy_src_fw_ov 79.000s 12308.207us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 79.000s 12308.207us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 207.000s 13035.071us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
entropy_src_intr 12.000s 502.875us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
entropy_src_functional_alerts 6.000s 713.564us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 82.000s 13666.546us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 52.964us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 7.000s 828.495us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 20.075us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 31.286us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 5.000s 147.576us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 5.000s 147.576us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 74.150us 1 1 100.00
entropy_src_csr_rw 1.000s 18.231us 1 1 100.00
entropy_src_csr_aliasing 3.000s 194.553us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 171.761us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 74.150us 1 1 100.00
entropy_src_csr_rw 1.000s 18.231us 1 1 100.00
entropy_src_csr_aliasing 3.000s 194.553us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 171.761us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 269.798us 1 1 100.00
entropy_src_tl_intg_err 4.000s 2606.825us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
entropy_src_cfg_regwen 2.000s 20.716us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
entropy_src_fw_ov 79.000s 12308.207us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 52.964us 1 1 100.00
entropy_src_sec_cm 3.000s 269.798us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 52.964us 1 1 100.00
entropy_src_sec_cm 3.000s 269.798us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 134.000s 13043.470us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 52.964us 1 1 100.00
entropy_src_sec_cm 3.000s 269.798us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 52.964us 1 1 100.00
entropy_src_sec_cm 3.000s 269.798us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 52.964us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 713.564us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 2606.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 155.000s 14042.042us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 9.000s 1452.424us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 38521746452706767107631464771424760692026314179569537891131998528736806223135 688
UVM_INFO @ 1452424170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* 1 test run
entropy_src_fw_ov 70724941672175650847893827933511379538452721005231107049220988893148999982204 1340
UVM_INFO @ 12308206959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 84910091101196438254986551605940473748115982874553480265586384122189155606329 113
UVM_INFO @ 26193943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---