Simulation Results: hmac

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.20 %
  • code
  • 95.95 %
  • assert
  • 97.17 %
  • func
  • 29.49 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.000s 1746.710us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 28.461us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 35.551us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.000s 2375.214us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.000s 107.936us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 43.313us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 35.551us 1 1 100.00
hmac_csr_aliasing 4.000s 107.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 93.000s 43930.408us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 10.000s 2020.535us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 164.000s 92288.646us 1 1 100.00
hmac_test_sha384_vectors 470.000s 19890.516us 1 1 100.00
hmac_test_sha512_vectors 22.000s 335.061us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 456.375us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 475.890us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 540.075us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.000s 521.509us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 108.000s 3401.797us 1 1 100.00
error 1 1 100.00
hmac_error 55.000s 7040.248us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 19.000s 672.517us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.000s 1746.710us 1 1 100.00
hmac_long_msg 93.000s 43930.408us 1 1 100.00
hmac_back_pressure 10.000s 2020.535us 1 1 100.00
hmac_datapath_stress 108.000s 3401.797us 1 1 100.00
hmac_burst_wr 7.000s 521.509us 1 1 100.00
hmac_stress_all 187.000s 24782.981us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.000s 1746.710us 1 1 100.00
hmac_long_msg 93.000s 43930.408us 1 1 100.00
hmac_back_pressure 10.000s 2020.535us 1 1 100.00
hmac_datapath_stress 108.000s 3401.797us 1 1 100.00
hmac_wipe_secret 19.000s 672.517us 1 1 100.00
hmac_test_sha256_vectors 164.000s 92288.646us 1 1 100.00
hmac_test_sha384_vectors 470.000s 19890.516us 1 1 100.00
hmac_test_sha512_vectors 22.000s 335.061us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 456.375us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 475.890us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 540.075us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.000s 1746.710us 1 1 100.00
hmac_long_msg 93.000s 43930.408us 1 1 100.00
hmac_back_pressure 10.000s 2020.535us 1 1 100.00
hmac_datapath_stress 108.000s 3401.797us 1 1 100.00
hmac_burst_wr 7.000s 521.509us 1 1 100.00
hmac_error 55.000s 7040.248us 1 1 100.00
hmac_wipe_secret 19.000s 672.517us 1 1 100.00
hmac_test_sha256_vectors 164.000s 92288.646us 1 1 100.00
hmac_test_sha384_vectors 470.000s 19890.516us 1 1 100.00
hmac_test_sha512_vectors 22.000s 335.061us 1 1 100.00
hmac_test_hmac256_vectors 14.000s 456.375us 1 1 100.00
hmac_test_hmac384_vectors 13.000s 475.890us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 540.075us 1 1 100.00
hmac_stress_all 187.000s 24782.981us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 187.000s 24782.981us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 87.068us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 45.518us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 177.971us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 177.971us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 28.461us 1 1 100.00
hmac_csr_rw 1.000s 35.551us 1 1 100.00
hmac_csr_aliasing 4.000s 107.936us 1 1 100.00
hmac_same_csr_outstanding 2.000s 195.591us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 28.461us 1 1 100.00
hmac_csr_rw 1.000s 35.551us 1 1 100.00
hmac_csr_aliasing 4.000s 107.936us 1 1 100.00
hmac_same_csr_outstanding 2.000s 195.591us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 43.024us 1 1 100.00
hmac_tl_intg_err 3.000s 173.750us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 173.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.000s 1746.710us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 232.365us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 113.000s 47663.374us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 36.569us 1 1 100.00