Simulation Results

Simulation Results: i2c

17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.38 %

code
85.69 %

assert
97.25 %

func
82.21 %

block
95.98 %

line
95.29 %

branch
92.78 %

toggle
72.68 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	90.000s	1069.968us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	18.000s	1979.719us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	42.080us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	15.795us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	2589.322us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	220.425us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	53.904us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	15.795us	1	1	100.00
	i2c_csr_aliasing	2.000s	220.425us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	54.855us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	30.000s	4127.124us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	21.000s	1765.390us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	15.062us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3601.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	773.000s	6567.892us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	97.082us	1	1	100.00
	i2c_host_fifo_fmt_empty	71.000s	2054.630us	1	1	100.00
	i2c_host_fifo_reset_rx	7.000s	231.359us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	645.000s	10420.127us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	14.000s	2774.686us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	4.000s	775.430us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	1750.054us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	41.000s	27776.804us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	568.032us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	31.000s	3960.010us	1	1	100.00
	i2c_target_intr_smoke	5.000s	3814.181us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	441.326us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	259.247us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	14.000s	22323.280us	1	1	100.00
	i2c_target_stress_rd	31.000s	3960.010us	1	1	100.00
	i2c_target_intr_stress_wr	3600.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.000s	5197.512us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	127.000s	4123.308us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.000s	2971.450us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	29.000s	10156.166us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	1287.422us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	620.710us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	21.000s	1765.390us	1	1	100.00
	i2c_host_perf_precise	45.000s	24521.411us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	14.000s	2774.686us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	178.162us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	585.744us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	1648.776us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	197.911us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	9.000s	299.483us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	500.799us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	18.110us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	40.078us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	127.947us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	127.947us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	42.080us	1	1	100.00
	i2c_csr_rw	2.000s	15.795us	1	1	100.00
	i2c_csr_aliasing	2.000s	220.425us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	86.671us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	42.080us	1	1	100.00
	i2c_csr_rw	2.000s	15.795us	1	1	100.00
	i2c_csr_aliasing	2.000s	220.425us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	86.671us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	113.600us	1	1	100.00
	i2c_sec_cm	1.000s	145.183us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	113.600us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	15.000s	546.950us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	388.588us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	2.000s	53.864us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	39180039474488723847337984404639635571556316247139678969884792478823715501741	105	UVM_INFO @ 54854994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	18733632645220031029554124278182563861602213084992727992048602607171842370584	102	UVM_INFO @ 4127124250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	76220438077326141714800152520228313044589907076529054888972745408380469157354	105	UVM_INFO @ 53864019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	i2c_host_fifo_watermark	5418806098558174254762961171037966848022444505448479260620801770649530855724	None
	i2c_target_intr_stress_wr	75706668515922587597047755369666398004600296150809946165871257032936287364343	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	26112559674119518510451824820541452523387872322091431282805708877276313643915	93	UVM_INFO @ 1750053802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	89234004119364758317841874989554008762899592417100194501380618337868497478294	87	UVM_INFO @ 388587915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	114276371747992049463115393013496715021966985511245726973854560982733633253563	88	UVM_INFO @ 10156165693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	108759026703136649794570323961023550101954665323654532495622620358004954225200	96	UVM_INFO @ 546949556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---