Simulation Results

Simulation Results: keymgr_dpe/darjeeling

17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
66.18 %

code
83.79 %

assert
97.18 %

func
17.56 %

block
97.93 %

line
98.64 %

branch
93.29 %

toggle
61.68 %

FSM
81.54 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%

V1

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	keymgr_dpe_smoke	12.000s	543.937us	1	1	100.00
csr_hw_reset				1	1	100.00
	keymgr_dpe_csr_hw_reset	2.000s	22.703us	1	1	100.00
csr_rw				1	1	100.00
	keymgr_dpe_csr_rw	2.000s	25.483us	1	1	100.00
csr_bit_bash				1	1	100.00
	keymgr_dpe_csr_bit_bash	4.000s	256.317us	1	1	100.00
csr_aliasing				1	1	100.00
	keymgr_dpe_csr_aliasing	5.000s	250.928us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	keymgr_dpe_csr_mem_rw_with_rand_reset	3.000s	86.008us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	keymgr_dpe_csr_rw	2.000s	25.483us	1	1	100.00
	keymgr_dpe_csr_aliasing	5.000s	250.928us	1	1	100.00

V2

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
intr_test				1	1	100.00
	keymgr_dpe_intr_test	1.000s	15.212us	1	1	100.00
alert_test				1	1	100.00
	keymgr_dpe_alert_test	2.000s	55.324us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	keymgr_dpe_tl_errors	3.000s	795.898us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	keymgr_dpe_tl_errors	3.000s	795.898us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	2.000s	22.703us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	25.483us	1	1	100.00
	keymgr_dpe_csr_aliasing	5.000s	250.928us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	3.000s	168.958us	1	1	100.00
tl_d_partial_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	2.000s	22.703us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	25.483us	1	1	100.00
	keymgr_dpe_csr_aliasing	5.000s	250.928us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	3.000s	168.958us	1	1	100.00

V2S

4/4 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	keymgr_dpe_sec_cm	5.000s	3961.040us	1	1	100.00
	keymgr_dpe_tl_intg_err	2.000s	323.922us	1	1	100.00
shadow_reg_update_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	48.717us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	48.717us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	48.717us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	48.717us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	keymgr_dpe_shadow_reg_errors_with_csr_rw	3.000s	136.451us	1	1	100.00
prim_count_check				1	1	100.00
	keymgr_dpe_sec_cm	5.000s	3961.040us	1	1	100.00
prim_fsm_check				1	1	100.00
	keymgr_dpe_sec_cm	5.000s	3961.040us	1	1	100.00