Simulation Results: lc_ctrl/volatile_unlock_disabled

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.86 %
  • code
  • 92.62 %
  • assert
  • 96.83 %
  • func
  • 86.13 %
  • block
  • 96.66 %
  • line
  • 97.35 %
  • branch
  • 91.49 %
  • toggle
  • 86.42 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 150.351us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 50.825us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 81.191us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 114.465us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 75.210us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 33.239us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 81.191us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 75.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 486.807us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 257.499us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 23.790us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 78.130us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 264.130us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 493.367us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 264.130us 1 1 100.00
lc_ctrl_prog_failure 3.000s 78.130us 1 1 100.00
lc_ctrl_errors 6.000s 493.367us 1 1 100.00
lc_ctrl_security_escalation 5.000s 2554.452us 1 1 100.00
lc_ctrl_jtag_state_failure 16.000s 1985.546us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 434.690us 1 1 100.00
lc_ctrl_jtag_errors 22.000s 16309.736us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 1896.941us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 16818.771us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 434.690us 1 1 100.00
lc_ctrl_jtag_errors 22.000s 16309.736us 1 1 100.00
lc_ctrl_jtag_access 4.000s 977.228us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.000s 935.859us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 117.760us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 143.474us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 8506.748us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 1577.481us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 40.594us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 360.009us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 30.808us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 13.000s 12020.495us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 14.576us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 18.000s 24490.237us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 23.322us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 1392.163us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 1392.163us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 50.825us 1 1 100.00
lc_ctrl_csr_rw 2.000s 81.191us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 75.210us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 30.208us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 50.825us 1 1 100.00
lc_ctrl_csr_rw 2.000s 81.191us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 75.210us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 30.208us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 943.735us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 133.602us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 133.602us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 257.499us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 264.130us 1 1 100.00
lc_ctrl_sec_cm 3.000s 943.735us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 264.130us 1 1 100.00
lc_ctrl_sec_cm 3.000s 943.735us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 264.130us 1 1 100.00
lc_ctrl_sec_cm 3.000s 943.735us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 264.130us 1 1 100.00
lc_ctrl_sec_cm 3.000s 943.735us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 264.130us 1 1 100.00
lc_ctrl_sec_cm 3.000s 943.735us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 264.130us 1 1 100.00
lc_ctrl_sec_cm 3.000s 943.735us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 264.130us 1 1 100.00
lc_ctrl_sec_cm 3.000s 943.735us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 264.130us 1 1 100.00
lc_ctrl_sec_cm 3.000s 943.735us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 2554.452us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 486.807us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 16818.771us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 979.743us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 979.743us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.000s 303.336us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 280.501us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 280.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 10.000s 5246.951us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 53018902055460670257279755503689551677068000702926403816227390012378993725787 2803
UVM_INFO @ 5246950959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---