Simulation Results: lc_ctrl/volatile_unlock_enabled

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.13 %
  • code
  • 93.27 %
  • assert
  • 96.69 %
  • func
  • 86.45 %
  • block
  • 97.07 %
  • line
  • 97.63 %
  • branch
  • 92.56 %
  • toggle
  • 87.63 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 48.432us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 72.466us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 53.388us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 96.376us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 68.625us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 20.955us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 53.388us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 68.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 76.984us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.000s 633.316us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.170us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 165.226us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 534.829us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 1106.346us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 534.829us 1 1 100.00
lc_ctrl_prog_failure 3.000s 165.226us 1 1 100.00
lc_ctrl_errors 4.000s 1106.346us 1 1 100.00
lc_ctrl_security_escalation 5.000s 475.190us 1 1 100.00
lc_ctrl_jtag_state_failure 17.000s 4940.146us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.000s 425.136us 1 1 100.00
lc_ctrl_jtag_errors 10.000s 2950.143us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 1121.899us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 280.002us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.000s 425.136us 1 1 100.00
lc_ctrl_jtag_errors 10.000s 2950.143us 1 1 100.00
lc_ctrl_jtag_access 7.000s 949.559us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 1111.174us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 206.105us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 137.685us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.000s 35159.223us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 206.185us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 46.165us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 214.858us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 78.422us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 278.666us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 22.408us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 21.000s 14418.497us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 56.105us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 155.291us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 155.291us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 72.466us 1 1 100.00
lc_ctrl_csr_rw 1.000s 53.388us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 68.625us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 46.163us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 72.466us 1 1 100.00
lc_ctrl_csr_rw 1.000s 53.388us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 68.625us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 46.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 292.197us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 232.501us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 232.501us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.000s 633.316us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 534.829us 1 1 100.00
lc_ctrl_sec_cm 2.000s 292.197us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 534.829us 1 1 100.00
lc_ctrl_sec_cm 2.000s 292.197us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 534.829us 1 1 100.00
lc_ctrl_sec_cm 2.000s 292.197us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 534.829us 1 1 100.00
lc_ctrl_sec_cm 2.000s 292.197us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 534.829us 1 1 100.00
lc_ctrl_sec_cm 2.000s 292.197us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 534.829us 1 1 100.00
lc_ctrl_sec_cm 2.000s 292.197us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 534.829us 1 1 100.00
lc_ctrl_sec_cm 2.000s 292.197us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 534.829us 1 1 100.00
lc_ctrl_sec_cm 2.000s 292.197us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 475.190us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 76.984us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 280.002us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1375.493us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1375.493us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 1130.732us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1802.563us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1802.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 22.000s 5637.724us 1 1 100.00