Simulation Results: otp_ctrl

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.38 %
  • code
  • 71.99 %
  • assert
  • 93.42 %
  • func
  • 51.73 %
  • line
  • 87.54 %
  • branch
  • 84.22 %
  • cond
  • 85.73 %
  • toggle
  • 64.51 %
  • FSM
  • 37.95 %
Validation stages
V1
100.00%
V2
65.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.110s 212.698us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.910s 496.692us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.080s 87.578us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.100s 126.651us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.120s 348.473us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 9.190s 395.741us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.700s 1914.551us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.100s 126.651us 1 1 100.00
otp_ctrl_csr_aliasing 9.190s 395.741us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.510s 631.645us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.370s 153.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 109.560s 11149.211us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.090s 153.400us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 14.310s 970.058us 0 1 0.00
otp_ctrl_check_fail 2.190s 899.815us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 14.630s 6932.931us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 10.580s 863.894us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 17.810s 9141.926us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 9.140s 678.576us 1 1 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 21.350s 1257.471us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 5.320s 283.651us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 2.890s 122.636us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 31.450s 2461.919us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.470s 94.720us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.070s 102.047us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.690s 130.705us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.690s 130.705us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.080s 87.578us 1 1 100.00
otp_ctrl_csr_rw 2.100s 126.651us 1 1 100.00
otp_ctrl_csr_aliasing 9.190s 395.741us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.720s 1589.791us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.080s 87.578us 1 1 100.00
otp_ctrl_csr_rw 2.100s 126.651us 1 1 100.00
otp_ctrl_csr_aliasing 9.190s 395.741us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.720s 1589.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
otp_ctrl_tl_intg_err 21.900s 3197.119us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 21.900s 3197.119us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.910s 496.692us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.910s 496.692us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
otp_ctrl_macro_errs 5.320s 283.651us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
otp_ctrl_macro_errs 5.320s 283.651us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.140s 901.499us 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.090s 153.400us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 2.190s 899.815us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 10.580s 863.894us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 10.580s 863.894us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 10.580s 863.894us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 10.580s 863.894us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 10.580s 863.894us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.910s 496.692us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 10.580s 863.894us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.910s 496.692us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 314.020s 24255.000us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 14.630s 6932.931us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.910s 496.692us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.910s 496.692us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 5.320s 283.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 110.710s 69029.624us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 12.000s 1786.740us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_check_fail 10093966656948557379575276312343507119987401014219350761696180206929770189172 468
UVM_INFO @ 899814842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 97837120363231058941382231836898849789094441884708586485207887885834179253295 1088
UVM_INFO @ 122636201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 98015892969337835941449279417985060128968849031116304327476393003669999383016 2417
UVM_INFO @ 1786739881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 87670351979182918015371501586145980819569849923383694831658903646966213372471 30987
UVM_INFO @ 2461919117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 3 test runs
otp_ctrl_background_chks 29561313897989487379782562866419245677906859294778148938781267191996999232862 11556
UVM_INFO @ 970057904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 98084384140061414887809422642955308122739432326459962166508988083227779187831 6173
UVM_INFO @ 863894188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 56464793401037587746920291853887856192996714127880141611210905567403542285468 15547
UVM_INFO @ 9141926379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_partition_walk 9682218884926829329089385285076449236477238390869048841306718754814451702692 160061
UVM_INFO @ 11149210908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 80692852078461954704549596165107436493198358122142377832255310672963270548763 95
UVM_INFO @ 69029624302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---