Simulation Results: rom_ctrl/32kb

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.46 %
  • code
  • 82.65 %
  • assert
  • 96.80 %
  • func
  • 91.92 %
  • block
  • 87.47 %
  • line
  • 89.60 %
  • branch
  • 80.93 %
  • toggle
  • 83.88 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 226.125us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 64.084us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 55.162us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 111.276us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 180.016us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 80.342us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 55.162us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 180.016us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 59.346us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.000s 77.055us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 9.966us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 5.000s 419.863us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 415.668us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 1.000s 78.753us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 209.651us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 209.651us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 64.084us 1 1 100.00
rom_ctrl_csr_rw 2.000s 55.162us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 180.016us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 85.812us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 64.084us 1 1 100.00
rom_ctrl_csr_rw 2.000s 55.162us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 180.016us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 85.812us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 18.000s 2054.982us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 178.695us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 43.000s 297.785us 1 1 100.00
rom_ctrl_tl_intg_err 19.000s 348.556us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 43.000s 297.785us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 43.000s 297.785us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 18.000s 2054.982us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 18.000s 2054.982us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 18.000s 2054.982us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 18.000s 2054.982us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 18.000s 2054.982us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 43.000s 297.785us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 43.000s 297.785us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 226.125us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 226.125us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 226.125us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 19.000s 348.556us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 18.000s 2054.982us 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 415.668us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 18.000s 2054.982us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 18.000s 2054.982us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 18.000s 2054.982us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 4.000s 178.695us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 43.000s 297.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 9.000s 1019.866us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 34740579463094081260414399918138570000640918647170751626136616356108865225616 88
UVM_INFO @ 9966018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 1 test run
rom_ctrl_stress_all_with_rand_reset 29530636510515302491343505253706858485311996857366506040219641567465986204127 94
UVM_INFO @ 1019866238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---