Simulation Results: rom_ctrl/64kb

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.23 %
  • code
  • 82.34 %
  • assert
  • 97.67 %
  • func
  • 96.67 %
  • block
  • 85.82 %
  • line
  • 87.26 %
  • branch
  • 81.16 %
  • toggle
  • 84.74 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 754.790us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 150.716us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 55.559us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 81.732us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 54.576us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 122.143us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 55.559us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 54.576us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 62.172us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 57.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 328.039us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.000s 1104.734us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 57.929us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 53.647us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 725.343us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 725.343us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 150.716us 1 1 100.00
rom_ctrl_csr_rw 2.000s 55.559us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 54.576us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 52.997us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 150.716us 1 1 100.00
rom_ctrl_csr_rw 2.000s 55.559us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 54.576us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 52.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 16516.529us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 6.000s 298.494us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 82.000s 1306.467us 1 1 100.00
rom_ctrl_tl_intg_err 19.000s 265.129us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 82.000s 1306.467us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 82.000s 1306.467us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 16516.529us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 16516.529us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 16516.529us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 16516.529us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 16516.529us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 82.000s 1306.467us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 82.000s 1306.467us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 754.790us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 754.790us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 754.790us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 19.000s 265.129us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 16516.529us 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 57.929us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 16516.529us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 16516.529us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 16516.529us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 6.000s 298.494us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 82.000s 1306.467us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 56.000s 8603.680us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 39975795868357811445368720821255492337717097081030807568985130379303435356359 88
UVM_INFO @ 328039193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---