Simulation Results: rstmgr

 
17/08/2026 16:37:20 DVSim: v1.50.1 sha: b9d39c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.74 %
  • code
  • 99.31 %
  • assert
  • 98.72 %
  • func
  • 98.19 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.52 %
  • toggle
  • 99.81 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.180s 69.206us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.190s 91.558us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.060s 38.048us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.450s 238.064us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.970s 37.529us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.480s 66.921us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.060s 38.048us 1 1 100.00
rstmgr_csr_aliasing 0.970s 37.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.890s 68.827us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.990s 47.748us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.220s 73.020us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.950s 598.778us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.950s 598.778us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.950s 598.778us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.950s 598.778us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 36.830s 5999.097us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.820s 37.584us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.430s 88.411us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.430s 88.411us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.190s 91.558us 1 1 100.00
rstmgr_csr_rw 1.060s 38.048us 1 1 100.00
rstmgr_csr_aliasing 0.970s 37.529us 1 1 100.00
rstmgr_same_csr_outstanding 1.570s 66.589us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.190s 91.558us 1 1 100.00
rstmgr_csr_rw 1.060s 38.048us 1 1 100.00
rstmgr_csr_aliasing 0.970s 37.529us 1 1 100.00
rstmgr_same_csr_outstanding 1.570s 66.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 31.770s 6795.641us 1 1 100.00
rstmgr_tl_intg_err 4.170s 646.729us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 31.770s 6795.641us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 31.770s 6795.641us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.170s 646.729us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.960s 58.272us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.400s 422.618us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.990s 291.483us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 31.770s 6795.641us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.060s 38.048us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.060s 38.048us 1 1 100.00